公开(公告)号：CA2064957A1

公开(公告)日：1992-12-29

申请号：CA2064957

申请日：1992-04-02

Applicant: IBM

Inventor： BASSO CLAUDE ,  CALVIGNAC JEAN

IPC: G06F13/00 ,  G06F15/16 ,  G06F17/30 ,  H04L29/00 ,  H04Q3/42

Abstract: FR9-90-031 METHOD AND APPARATUS FOR PERFORMING PATTERN SEARCH FUNCTIONS A method and apparatus for searching a pattern such as an address pattern of 48 bits among a list of addresses of 48 bits which can be dynamically updated. A search table comprising control blocks is used for conducting the search of a specified pattern by processing logic circuits. The control blocks can be of a first type indicative of test operations on at least one selected bit of the to- besearched pattern and of of a second type indicative of compare operations with a specified value and of a third type indicative that no operations have to be performed. These control blocks are chained in at least one chain in such a way that each control block chain determine operations which lead to the finding of one of the p patterns. To perform the search, a processing logic circuit reads a first control block at a search table address which is derived from a selected field of k=12 bits of the pattern to be searched. It generates a not-found pattern signal if the read control block is of the third type, or executes the the operations indicated in the first read control block and the control blocks chained thereto, until a control block of the second type is is reached and compares the to be searched pattern with the specified value in the control block of the second type. If a mismatch is detected, it generates a "not found pattern" information and if a match is detected it generates a a "found pattern" information.

公开(公告)号：DE3685587D1

公开(公告)日：1992-07-09

申请号：DE3685587

申请日：1986-08-27

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  SECONDO PIERRE

IPC: H04L12/64 ,  H04L12/56 ,  H04L12/00

Abstract: The transport mechanism has a storage device (11,12) in which queues of storing positions are assinged to the circuit uses attached to a node, into which the circuit user information to be sent on the network intermode lnks (L1,L2) and received from the network inter-node links are stored. A intermode adapting circuit controls the generation and the reception of the frames to and from each intermode link operating under control fo the node management circuit. The management circuit assigns on the call basis, a set of at least one slot in the frames transported on the network line to several circuit users, and which comprise transmit and receive controllers (24-T, 26-T, 20-R, 22-R, 28). The transmit controller cause the queues assigned, to be sequenitally scanned and read. The receive controller causes the information received to be written into the queues assigned tothe users which are sequentially scanned, when the qualification bis are found equal to the first value.

公开(公告)号：CA1250935A

公开(公告)日：1989-03-07

申请号：CA505860

申请日：1986-04-04

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  SECONDO PIERRE

IPC: H04L12/64 ,  H04Q11/04 ,  H04L11/20

Abstract: System to be used for dynamically allocating circuit slots in the frames which are used for exchanging bits between users connected to nodes of a communication network linked by means of medium links having transmit and receive interfaces, said frames being delimited by flags and divided into bit slots which may be devoted to synchronous circuit flow and to asynchronous packet flow. It comprises in each node means for changing the flags preceding at least one frame in which at least one slot is to be added or deleted to a value including a first number of delimiting bits and a second number of bits which are coded to indicate that slot(s) is (are) to be added or deleted and the corresponding slot number(s); means for sending call control packets which are propagated through the network nodes, comprising call control information , routing information and indicating the circuit user slot number(s) to be added or deleted on specified link interfaces, and means receiving the call control packets and the changed flags for adding or deleting circuit user slot(s) in the subsequent frames depending upon the flag value. Figure 11

公开(公告)号：DE112011104491T5

公开(公告)日：2013-10-24

申请号：DE112011104491

申请日：2011-12-19

Applicant: IBM

Inventor： PORET MICHEL LOUIS RAYMOND ,  BASSO CLAUDE ,  PHILIPPE DAMON ,  VERRILLI COLIN ,  CALVIGNAC JEAN ,  CHANG CHIH-JEN ,  VAIDHYANATHAN NATARAJAN ,  VERPLANKEN FABRICE JEAN

IPC: G06F5/10 ,  G06F13/12

Abstract: Die Erfindung stellt ein Verfahren zum Hinzufügen spezifischer Hardware sowohl auf der Empfangs- als auch auf der Sendeseite bereit, die den größten Teil des Aufwands in Bezug auf die Puffer- und Zeigerverwaltung vor der Software verbirgt. Bei der Initialisierung wird von Software ein ausreichend großer Satz von Zeigern und Puffern bereitgestellt, um den erwarteten Datenverkehr unterstützen zu können. Eine Sendewarteschlange-Auffülleinrichtung (SQR) und eine Empfangswarteschlangen-Auffülleinrichtung (RQR) verbergen die RQ- und SQ-Verwaltung vor der Software. Die RQR und die SQR überwachen umfassend Zeigerwarteschlangen und führen die Rückführung von Zeigern von der Sendeseite zur Empfangsseite aus.

公开(公告)号：DE60033529T2

公开(公告)日：2007-11-15

申请号：DE60033529

申请日：2000-08-24

Applicant: IBM

Inventor： BASS BRIAN ,  CALVIGNAC JEAN ,  HEDDES MARCO ,  PATEL PIYUSH ,  REVILLA JUAN ,  SIEGEL MICHAEL ,  VERPLANKEN FABRICE

IPC: G06F15/16 ,  G06F15/167 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F15/177 ,  H04L12/56 ,  H04Q11/04

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.

公开(公告)号：DE60205231T2

公开(公告)日：2006-05-24

申请号：DE60205231

申请日：2002-03-28

Applicant: ALCATEL SA ,  IBM

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

公开(公告)号：AU2002242874A1

公开(公告)日：2002-10-21

申请号：AU2002242874

申请日：2002-03-28

Applicant: IBM

Inventor： VRANA MIROSLAV ,  CALVIGNAC JEAN ,  VERPLANKEN FABRICE ,  BARRI PETER ,  LOGAN JOSEPH ,  HEDDES MARCO ,  NIEMEGEERS ALEX

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

公开(公告)号：DE69329709D1

公开(公告)日：2001-01-04

申请号：DE69329709

申请日：1993-04-29

Applicant: IBM

Inventor： BASSO CLAUDE ,  CALVIGNAC JEAN ,  GALAND CLAUDE ,  GIROIRD DIDIER ,  VERPLANKEN FABRICE

IPC: G06F13/00 ,  G06F15/16 ,  G06F15/177 ,  H04L12/18

Abstract: A communications system comprises a memory which is shared by a plurality of users, each one receiving and transmitting messages to each other. In the present system, a message is composed of a plurality of data buffers stored in the memory and each data buffer is controlled and mapped to a unique direct control block (DCB) which stores the characteristics of said data buffer. The chaining of the DCB forms the whole message which may be multicast to a plurality of users. Therefore, in order to improve the performance of such communications system, one may duplicate the message as many times as necessary without re-writing the data in the personal storage of each user by using an indirect control block (ICB) which represents the message duplicated. Each ICB stores the characteristics of the message duplicated and points to a DCB. A field in the DCB enables to count the number of duplication of the message. The DCB and ICB stores different fields which are required in order to perform the operations of lease control block from the free queues, the operations of message enqueue in the user queue, the operations of message dequeue from the user queue, and the operations of message release to the free queues. Two separate free queues FDCBQ and FICBQ chaining the free DCB and ICB are provided and are controlled by two control blocks FDQCB and FIQCB. The present apparatus and method may also be used for multicasting data buffer which composes a message by adding new fields in the ICB. In this case, the message to be multicast may have a content different from the original one, which requires therefore that to each ICB correspond a unique DCB.

公开(公告)号：DE69021712T2

公开(公告)日：1996-04-18

申请号：DE69021712

申请日：1990-02-08

Applicant: IBM

Inventor： ALAIWAN HAISSAM ,  BASSO CLAUDE ,  CALVIGNAC JEAN ,  COMBES JACQUES ,  KERMAREC FRANCOIS ,  PAUPORTE ANDRE

IPC: G06F11/14 ,  G06F11/20 ,  G06F15/16

Abstract: A checkpointing mechanism implemented in a data processing system comprising a dual processor configuration gives the system a fault tolerance capability while minimizing the complexity of both the software and the hardware. The active and backup processors are coupled asynchronously with some hardware assist functions comprising a memory change detector which captures the memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establish recovery point signals generated by the active processor to be dumped into the memory of the back up processor so that the backup processor can resume the operations of the active processor from the last established recovery point. The active and backup processors may each be connected to a dedicated memory and recovery point storing means, or to a memory including two dual sides shared by all the processors for storing data structures and recovery points.

公开(公告)号：DE69022025D1

公开(公告)日：1995-10-05

申请号：DE69022025

申请日：1990-03-13

Applicant: IBM

Inventor： BARUCCHI GERARD ,  GALCERA JOSE ,  TOUBOL GILLES ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

IPC: G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

Abstract: The synchronization circuit resynchronizes the data bits received from remote devices from line or link 20-1 with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in a n-bit cyclic buffer (114-1) with the received bit clock CS and they are sequentially picked at the opposite buffer position with the central clock CO The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.