公开(公告)号：DE3851038T2

公开(公告)日：1995-03-09

申请号：DE3851038

申请日：1988-10-20

Applicant: IBM

Inventor： CHANG ALBERT ,  COCKE JOHN ,  MERGEN MARK FREDERICK ,  OEHLER RICHARD RAPHAEL

IPC: G06F12/00 ,  G06F12/14

Abstract: A method of and a controller for accessing a protected memory which is logically divided into major partitions - pages - which are in turn sub-divided into minor partitions - blocks - by concurrently executing transactions, using virtual block addressing and address translation at the memory controller via an access table, wherein there are provided table entries containing priviledged access control fields relating to the pages and lock fields relating to the individual blocks, by receiving an address of a data block to be accessed by an identifiable transaction; deriving from the address an access table entry corresponding to the data block and testing the data in the page access control field and the lock field governing access to the block; and providing the requested access if permitted by the access control data and the lock data for the type of access concerned, and also providing recorded access, if not permitted but not specifically denied by the lock data, using at least part of the lock field to record such latter type of access.

公开(公告)号：DE3485929D1

公开(公告)日：1992-10-29

申请号：DE3485929

申请日：1984-05-30

Applicant: IBM

Inventor： AUSLANDER MARC ALAN ,  COCKE JOHN ,  HAO HSIEH TUNG ,  MARKSTEIN PETER WILLY ,  RADIN GEORGE

IPC: G06F9/30 ,  G06F7/493 ,  G06F7/50 ,  G06F9/302 ,  G06F9/305 ,  G06F9/32 ,  G06F9/46

Abstract: @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.

公开(公告)号：DE3586374D1

公开(公告)日：1992-08-27

申请号：DE3586374

申请日：1985-07-16

Applicant: IBM

Inventor： AUSLANDER MARC ALAN ,  COCKE JOHN ,  MARKSTEIN PETER WILLY

IPC: G06F9/44 ,  G06F9/45

公开(公告)号：DE3063100D1

公开(公告)日：1983-06-16

申请号：DE3063100

申请日：1980-06-24

Applicant: IBM

Inventor： COCKE JOHN ,  MALM RICHARD LAVERNE ,  SHEDLETSKY JOHN JAMES

IPC: G06F11/25 ,  G01R31/28 ,  G06F15/00 ,  G06F17/50 ,  G06F15/20 ,  G06F15/16

Abstract: A computer system for simulation of logic operations comprised of an array of specially designed parallel processors (1-31), there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory (202). Logic values simulated by one processor are communicated to other processors by a switching mechanism (33) controlled by a controller (32). If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks (35, 36) for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks (38, 39) are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.

公开(公告)号：CA986232A

公开(公告)日：1976-03-23

申请号：CA179114

申请日：1973-08-16

Applicant: IBM

Inventor： COCKE JOHN ,  HELMAN DAVID R

IPC: G06F9/32 ,  G06F9/22 ,  G06F9/24 ,  G06F9/34 ,  G06F12/10

公开(公告)号：DE2339636A1

公开(公告)日：1974-04-04

申请号：DE2339636

申请日：1973-08-04

Applicant: IBM

Inventor： HELMAN DAVID ROBERT ,  COCKE JOHN

IPC: G06F9/32 ,  G06F9/22 ,  G06F9/24 ,  G06F9/34 ,  G06F12/10 ,  G05B19/00

公开(公告)号：DE1774571A1

公开(公告)日：1971-12-02

申请号：DE1774571

申请日：1968-07-18

Applicant: IBM

Inventor： COCKE JOHN ,  VISVALD FREIMAN CHARLES ,  EDWARD HOMAN MERLE

IPC: G06F7/52 ,  G06F7/535

Abstract: 1,177,608. Dividers; data storage. INTERNATIONAL BUSINESS MACHINES CORP 20 June, 1968 [19 July, 1967], No. 29364/68. Headings G4A and G4C. Division of a multi-order dividend by a predetermined divisor is done by concurrently generating a plurality of intermediate remainders relating to respective orders, combining each dividend order with the next higher order intermediate remainder and dividing the result by the predetermined divisor. Figs. 12A, 12B show division of an octal number by a fixed divisor equal to 3. Each quotient digit is generated in a respective circuit 130, 132 which divides its input by 3 and discards the remainder. In the case of the highest order digit, this input is the highest order dividend digit (circuit 130) but in the other cases (circuits 132) it is a two-digit octal number formed by the corresponding dividend digit (as low-order digit) concatenated with a one-digit intermediate remainder obtained from higher order dividend digits as shown using circuits 134, 126, 128. Each circuit 134 casts out threes from a corresponding dividend digit. Each circuit 126 subtracts its left input from its upper input and casts out threes from the result (i.e. is a modulo-3 subtractor), and each circuit 128 adds its two inputs and casts out threes from the result (i.e. is a modulo-3 adder). Each octal digit is binary-coded so the dividend is also binary. Similar circuits are described for a radix 10, divisor 7 division, radix 8, divisor 7, radix 10, divisor 5, and radix 16, divisor 5 (the 16 is binary-coded so the dividend is also binary radix). Each circuit corresponding to 126, 128 in effect multiplies its left input by (R modulo D) Y modulo D, the least positive or negative value being used, where D is the divisor, R the radix and Y the number of orders the input has traversed from its generation point. The resulting product is added to the upper input and the result, modulo the divisor, is the circuit output. In some embodiments, the quantity "R modulo D" is one in which case the multiplication stage is dispensed with, or even zero in which case circuits corresponding to 126, 128 are completely absent. The above embodiments may be preceded by a shift register permitting a preliminary further division by a power of 2 by shifting. Data storage.-In a memory system having a plurality of data words per memory word, the divider above may be used to divide the data word address, the quotient being used to address the memory word and the remainder to select the data word from the memory word.

公开(公告)号：DE68924477D1

公开(公告)日：1995-11-09

申请号：DE68924477

申请日：1989-12-12

Applicant: IBM

Inventor： COCKE JOHN ,  MONTOYE ROBERT KEVIN

IPC: G06F7/487 ,  G06F7/527 ,  G06F7/53 ,  G06F7/544 ,  G06F7/48

公开(公告)号：DE3751306D1

公开(公告)日：1995-06-22

申请号：DE3751306

申请日：1987-10-27

Applicant: IBM

Inventor： COCKE JOHN ,  MARKSTEIN PETER WILLY

IPC: G06F9/45 ,  G06F9/44

公开(公告)号：DE3382307D1

公开(公告)日：1991-07-11

申请号：DE3382307

申请日：1983-12-22

Applicant: IBM

Inventor： CHANG ALBERT ,  COCKE JOHN ,  MERGEN MARK ,  RADIN GEORGE

IPC: G06F13/00 ,  G06F11/07 ,  G06F12/00 ,  G06F12/10 ,  G06F12/14

Abstract: A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memories wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address. Also included in apparatus for sequentially searching through the linked group of virtual addresses in the combined table until a selected virtual address is located as well as apparatus responsive to the location of a particular selected virtual address for accessing from the first list, the real memory address of the located virtual address.