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    Data processing
    21.
    发明专利
    Data processing 未知

    公开(公告)号：GB2502663B

    公开(公告)日：2014-07-30

    申请号：GB201303302

    申请日：2013-02-25

    Applicant: IBM

    Inventor： GHAI SANJEEV ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  STUECHELI JEFFREY ,  WILLIAMS DEREK ,  WILLIAMS PHILIP

    IPC: G06F12/12 ,  G06F12/08

    Abstract: In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.

    23.
    发明专利
    未知

    公开(公告)号：DE19782087B4

    公开(公告)日：2010-05-20

    申请号：DE19782087

    申请日：1997-09-30

    Applicant: IBM

    Inventor： GUTHRIE GUY LYNN ,  NEAL DANNY MARVIN ,  KELLEY RICHARD ALLEN

    IPC: G06F13/40

    Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).

    25.
    发明专利
    未知

    公开(公告)号：DE69736872D1

    公开(公告)日：2006-12-14

    申请号：DE69736872

    申请日：1997-03-20

    Applicant: IBM

    Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

    IPC: G06F13/40 ,  G06F13/36

    Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.

    Forward progress mechanism for stores in the presence of load contention in a system favoring loads
    28.
    发明专利
    Forward progress mechanism for stores in the presence of load contention in a system favoring loads 未知

    公开(公告)号：GB2512804B

    公开(公告)日：2015-03-04

    申请号：GB201414384

    申请日：2013-01-23

    Applicant: IBM

    Inventor： WILLIAMS DEREK EDWARD ,  GUTHRIE GUY LYNN ,  LE HIEN MINH ,  STUECHELI JEFFREY A

    IPC: G06F12/08 ,  G06F15/167

    Abstract: A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.

    Handling of Deallocation Requests in System Having Upper and Lower Level Caches
    30.
    发明专利
    Handling of Deallocation Requests in System Having Upper and Lower Level Caches 未知

    公开(公告)号：GB2502662A

    公开(公告)日：2013-12-04

    申请号：GB201303300

    申请日：2013-02-25

    Applicant: IBM

    Inventor： GHAI SANJEEV ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  STUECHELI JEFFREY ,  WILLIAMS DEREK EDWARD ,  WILLIAMS PHILIP

    IPC: G06F12/12 ,  G06F12/08

    Abstract: A deallocate request specifying a target address associated with a target cache line is sent from processor core to lower level cache; if the request hits the replacement order of the lower level cache is updated such that the target is more likely to be evicted (e.g. making the target line least recently used [LRU]) in response to a subsequent cache miss. The replacement order may not be updated with further accesses to target cache line prior to eviction. The lower cache may include load and store pipelines, with deallocation requests sent to the load pipeline. The deallocate instruction may be executed at completion dataset processing, and may be sent to lower level cache regardless of hitting in the upper cache. Lower cache may include state machines servicing data requests, with retaining and updating performed without allocation of state machine/s to the request. A compiler may insert the deallocation instruction into program code executed by the processor core, in response to the detection of an end of dataset processing. An interconnect fabric may couple the processing units.

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