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    Lithographieprozess mit doppelter Hartmaske
    21.
    发明专利
    Lithographieprozess mit doppelter Hartmaske 未知

    公开(公告)号：DE112012005734T5

    公开(公告)日：2014-11-13

    申请号：DE112012005734

    申请日：2012-12-20

    Applicant: IBM

    Inventor： ARNOLD JOHN C ,  BURNS SEAN D ,  HOLMES STEVEN J ,  HORAK DAVID V ,  SANKARAPANDIAN MUTHUMANICKAM ,  YIN YUNPENG

    IPC: H01L21/027 ,  G03F1/68 ,  G03F1/80 ,  G03F7/20

    Abstract: Eine erste metallische Hartmaskenschicht über einer dielektrischen Zwischenverbindungsebenen-Schicht wird mit einem Leitungsmuster strukturiert. Oberhalb der ersten metallischen Hartmaskenschicht wird wenigstens eine Schicht aus einem dielektrischen Material, eine zweite metallische Hartmaskenschicht, eine erste organische Planarisierungsschicht (OPL) sowie ein erstes Photoresist angebracht. Ein erstes Durchkontakt-Muster wird von der ersten Photoresistschicht in die zweite metallische Hartmaskenschicht hinein transferiert. Eine zweite OPL und ein zweites Photoresist werden angebracht und mit einem zweiten Durchkontakt-Muster strukturiert, das in die zweite metallische Hartmaskenschicht hinein transferiert wird. Ein erstes Kombinationsmuster aus dem ersten und dem zweiten Durchkontaktmuster wird in die wenigstens eine Schicht aus einem dielektrischen Material transferiert. Ein zweites Kombinationsmuster, welches das erste Kombinationsmuster mit den Gebieten der Öffnungen in der ersten metallischen Hartmaskenschicht begrenzt, wird in die dielektrische Zwischenverbindungsebenen-Schicht hinein transferiert.

    Low-profile local interconnect and method of making the same
    22.
    发明专利
    Low-profile local interconnect and method of making the same 未知

    公开(公告)号：GB2507011A

    公开(公告)日：2014-04-16

    申请号：GB201401202

    申请日：2012-03-12

    Applicant: IBM

    Inventor： PONOTH SHOM ,  HORAK DAVID V ,  KOBURGER CHARLES W ,  YANG CHIH-CHAO

    IPC: H01L21/768

    Abstract: Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect- transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.

    Low-profile local interconnect and method of making the same
    24.
    发明专利
    Low-profile local interconnect and method of making the same 未知

    公开(公告)号：GB2507011B

    公开(公告)日：2015-06-10

    申请号：GB201401202

    申请日：2012-03-12

    Applicant: IBM

    Inventor： PONOTH SHOM ,  HORAK DAVID V ,  KOBURGER CHARLES W ,  YANG CHIH-CHAO

    IPC: H01L21/8234

    Abstract: Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.

    METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICES FORMED THEREBY
    26.
    发明专利
    METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICES FORMED THEREBY 未知

    公开(公告)号：MY117065A

    公开(公告)日：2004-04-30

    申请号：MYPI9904306

    申请日：1999-10-06

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: H01L21/22 ,  H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/425 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/78

    Abstract: THE PRESENT INVENTION PROVIDES A METHOD FOR FORMING SELF-ALIGNED SPACERS (502) ON THE HORIZONTAL SURFACES WHILE REMOVING SPACER MATERIAL FROM THE VERTICAL SURFACES. THE PREFERRED METHOD USES A RESIST(302) THAT CAN BE MADE INSOLUBLE TO DEVELOPER BY THE USE OF AN IMPLANT. BY CONFORMALLY DEPOSITING THE RESIST OVER A SUBSTRATE (202) HAVING BOTH VERTICAL AND HORIZONTAL SURFACES, IMPLANTING THE RESIST, AND DEVELOPING THE RESIST, THE RESIST IS REMOVED FROM THE VERTICAL SURFACES WHILE REMAINING ON THE HORIZONTAL SURFACES. THUS, A SELF-ALIGNED SPACER IS FORMED ON THE HORIZONTAL SURFACES WHILE THE SPACER MATERIAL IS REMOVED FROM THE VERTICAL SURFACES. THIS HORIZONTAL-SURFACE SPACER CAN THEN BE USED IN FURTHER FABRICATION. THE PREFERRED METHOD CAN BEUSED IN MANY DIFFERENT PROCESSES WHERE THERE IS EXISTS A NEED TO DIFFERENTIALLY PROCESS THE VERTICAL AND HORIZONTAL SURFACES OF A SUBSTRATE.FIG. 1

    Dual hard mask lithography process
    29.
    发明专利
    Dual hard mask lithography process 未知

    公开(公告)号：GB2511456A

    公开(公告)日：2014-09-03

    申请号：GB201410024

    申请日：2012-12-20

    Applicant: IBM

    Inventor： BURNS SEAN D ,  HOLMES STEVEN J ,  HORAK DAVID V ,  SANKARAPANDIAN MUTHUMANICKAM ,  YIN YUNPENG ,  ARNOLD JOHN C

    IPC: H01L21/033 ,  G03F7/00 ,  H01L21/768

    Abstract: A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

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