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    Verfahren und System zur kontinuierlichen Bereitstellung eines Präzisionssystemakts
    22.
    发明专利
    Verfahren und System zur kontinuierlichen Bereitstellung eines Präzisionssystemakts 未知

    公开(公告)号：DE102012203531A1

    公开(公告)日：2012-09-27

    申请号：DE102012203531

    申请日：2012-03-06

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  VON BUTTLAR JOACHIM ,  LEHNERT FRANK ,  ENGLER EBERHARD ,  MEISSNER KLAUS

    IPC: G06F1/04

    Abstract: Die Erfindung betrifft ein Verfahren zur kontinuierlichen Bereitstellung eines Präzisionssystemtakts, der einem Prozessorkern (2) zugeordnet ist, wobei der Systemtakt ein Host-Taktregister (5) umfasst, das mithilfe eines Präzisionsoszillators aktualisiert wird, das Verfahren die Schritte des Bereitstellens eines Firmware-Taktregisters (6), des Hochzählens des Firmware-Taktregisters (6) bei jedem Hochzählen des Host-Taktregisters (5), der Überwachung von Ausfällen des Host-Taktregisters (5) und bei einem Ausfall des Host-Taktregisters (5) das kontinuierliche Hochzählen des Firmware-Taktregisters (6) mithilfe von Zeitsignalen des Prozessorkerns (2) sowie bei Empfang einer Anforderung auf Bereitstellung eines Taktwertes das Bereitstellen des Inhalts des Host-Taktregisters (5) umfasst, wenn kein Ausfall festgestellt wurde, und andernfalls den Inhalt des Firmware-Taktregisters (6).

    Updating corrupted local working registers in a multi-staged pipelined execution unit by refreshing from the last state hold a global checkpoint array
    23.
    发明专利
    Updating corrupted local working registers in a multi-staged pipelined execution unit by refreshing from the last state hold a global checkpoint array 未知

    公开(公告)号：GB2456891A

    公开(公告)日：2009-08-05

    申请号：GB0823186

    申请日：2008-12-19

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  MAYER ULRICH ,  LEHNERT FRANK ,  SHUM KEVIN CHUNG-LUNG

    IPC: G06F9/38 ,  G06F11/00

    Abstract: Disclosed is a method for updating corrupted local working registers in a multi-staged pipeline structure, after an exception. The registers being needed to execute complex instructions in an execution unit, e.g. a floating-point unit, whose deep pipeline structure comprises a set of local working registers. The pipeline being such data dependencies among different instructions referencing the same registers exist. The method operates by refreshing any corrupted local working register from the last architected state hold in a global checkpoint array. The registers may also be updated using the hardware infrastructure of the execution unit when the data is corrupted by early pipeline updates. A master copy of all local working registers may be held in the checkpoint array, which is not updated in exception cases. All the early loads or early register updates form instructions that were issued after an instruction got into the exception may be refreshed.

    Clock gating system for macro circuits on a semiconductor chip
    24.
    发明专利
    Clock gating system for macro circuits on a semiconductor chip 未知

    公开(公告)号：GB2456202A

    公开(公告)日：2009-07-08

    申请号：GB0821970

    申请日：2008-12-02

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  LEHNERT FRANK ,  MAYER ULRICH

    IPC: G06F1/10 ,  G06F1/32

    Abstract: A digital circuit on a semiconductor chip comprises a plurality of macro circuits (10, 12, 14) and a clock gating system (50, 52, 54) for disabling the clock signal for at least one single macro circuit (12) to reduce power consumption. The circuit comprises a hierarchical structure with at least two clock gating levels, and each macro circuit (10, 12, 14) is associated with one of the levels. A macro control circuit (10) is provided on a top clock gating level and controls the clock gating of at least one other macro circuit (12) on one or more lower clock gating levels, wherein all external signals used to control the clock gating are connected to the control circuit (10). The method distinguishes between two clock gating granularities. A coarse-grain gating operates on the boundaries of the macro circuits, and a fine-grain gating operates mainly on dataflow storage elements within the macro circuits.

    Handling an input/output store instruction
    25.
    发明专利
    Handling an input/output store instruction 未知

    公开(公告)号：AU2020213829B2

    公开(公告)日：2022-09-15

    申请号：AU2020213829

    申请日：2020-01-14

    Applicant: IBM

    Inventor： RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  BELMAR BRENTON ,  DRIEVER PETER

    IPC: G06F9/30 ,  G06F13/20

    Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to at least one external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed. The asynchronous core-nest interface (14) comprises an input/output status array (44) with multiple input/output status buffers (24).

    HANDLING AN INPUT/OUTPUT STORE INSTRUCTION
    26.
    发明专利
    HANDLING AN INPUT/OUTPUT STORE INSTRUCTION 未知

    公开(公告)号：CA3127852A1

    公开(公告)日：2020-08-06

    申请号：CA3127852

    申请日：2020-01-14

    Applicant: IBM

    Inventor： RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  BELMAR BRENTON ,  DRIEVER PETER

    IPC: G06F9/30 ,  G06F13/00 ,  G06F13/20

    Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to an external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed.

    Updating of shadow registers in N:1 clock domain
    27.
    发明专利
    Updating of shadow registers in N:1 clock domain 未知

    公开(公告)号：GB2528481A

    公开(公告)日：2016-01-27

    申请号：GB201413052

    申请日：2014-07-23

    Applicant: IBM

    Inventor： KOEHLER THOMAS ,  LEHNERT FRANK

    IPC: G06F9/30 ,  G06F5/06 ,  G06F13/40

    Abstract: A processing unit comprises a first storage entity 2 updated at a first clock cycle CLK1 holding a master copy of the processing unit state, and at least two shadow storage entities 3, 3a, 3b being updated with update information of the first storage entity, the shadow storage entity running at a second clock cycle CLK2 slower than the first. The first storage entity is coupled with the shadow storage entities via an intermediate storage entity 4 which provides multiple storage stages 4.1, 4.2, 4.3, 4.4 for buffering consecutive update information. A selection circuitry 5 provides one update information contained in one storage stage to the shadow storage entity with the active clock edge of the second clock cycle to update it. This facilitates efficient and reliable transfer of update information to shadow registers running at a slower clock cycle.

    Erzeugen von monoton ansteigenden TOD-Werten in einem Multiprozessorsystem
    29.
    发明专利
    Erzeugen von monoton ansteigenden TOD-Werten in einem Multiprozessorsystem 未知

    公开(公告)号：DE102013209625A1

    公开(公告)日：2013-12-05

    申请号：DE102013209625

    申请日：2013-05-23

    Applicant: IBM

    Inventor： JACOBI CHRISTIAN ,  SLEGEL TIMOTHY J ,  GERWIG GUENTER ,  SHUM CHUNG-LUNG KEVIN ,  LEHNERT FRANK

    IPC: G06F1/12

    Abstract: Ein Verfahren zum Erzeugen von monoton ansteigenden Zeitwerten in einem Multiprozessorsystem kann bereitgestellt werden. Das Verfahren kann das Empfangen von Synchronisationsimpulsen durch einen Prozessor des Multiprozessorsystems und das Verweigern einer Ausführung eines Lesebefehls eines TOD-Wertes in einem Prozessor der Prozessoren aufweisen, wenn die Ausführung des Lesebefehls des TOD-Wertes nach einem vorher festgelegten Zeitraum im Anschluss an einen Synchronisationsimpuls der Synchronisationsimpulse angefordert wird und wenn nach dem vorher festgelegten Zeitraum ein Triggersignal empfangen wurde, das anzeigt, dass von einem zugehörigen Speichersystem neue Daten empfangen worden sind, wobei sich das Speichersystem außerhalb des Prozessors befindet.

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