公开(公告)号：WO0203423A3

公开(公告)日：2002-08-08

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供了一种DRAM单元和制造方法，其通过将堆叠的电容器形成与电触点并入来消除关键的光刻制造步骤。 由于层叠的电容器（46,48,50）与位线（36）是共面的，所以单个光刻步骤可用于形成电触点（28），并且堆叠的电容器位于设置在 位线。 与常规的电容器位线（COB）DRAM单元不同，这种位线旁边的DRAM电池消除了将触点专用于电容器的需要，使得可以在较低的全局地形下实现更高的电容。

公开(公告)号：WO0237542A2

公开(公告)日：2002-05-10

申请号：PCT/US0146921

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  KUDELKA STEPHAN

IPC: H01L21/8242 ,  H01L21/00

CPC classification number: H01L27/10867 ,  H01L27/10876

Abstract: A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.

Abstract translation: 形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

公开(公告)号：JP2004193588A

公开(公告)日：2004-07-08

申请号：JP2003389984

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEWIS L SUU ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: G11C11/412 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM cell design capable of simultaneously attaining high performance, low power, and small chip size by using only vertical MOSFET device including a peripheral (transmission) gate. SOLUTION: A method for forming a SRAM cell device comprises the steps of forming a pass gate FET transistor in a silicon layer formed on a flat insulating material and a parallel island, and further forming a pair of vertical pulldown FET transistors having a first common body and a first common source region. The method further forms a pulldown separation space for dividing an upper layer of a pullup and pulldown drain region of a pair of vertical pulldown FET transistor in two by etching through the upper diffusion between cross-linked inverter FET transistors, and the separation space reaches the common boby layer. The method further comprises the steps of forming a pair of vertical pullup FET transistor having a second common body and a second common drain, and connecting the FET transistor so as to form a SRAM cell. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：通过仅使用包括外围（传输）门的垂直MOSFET器件，提供能够同时获得高性能，低功率和小芯片尺寸的SRAM单元设计。 解决方案：一种用于形成SRAM单元器件的方法包括以下步骤：在形成于平坦绝缘材料和平行岛上的硅层中形成栅极FET晶体管，并进一步形成一对垂直下拉FET晶体管，其具有 第一共同体和第一共同源区。 该方法进一步形成一个下拉分离空间，用于通过在交联的反相FET晶体管之间的上部扩散进行蚀刻，将一对垂直下拉式FET晶体管的上拉和下拉漏极区的上层分成两层，分离空间达到 普通boby层。 该方法还包括以下步骤：形成具有第二公共体和第二公共漏极的一对垂直上拉FET晶体管，并连接FET晶体管以形成SRAM单元。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2003023155A

公开(公告)日：2003-01-24

申请号：JP2002127052

申请日：2002-04-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS L ,  RADENS CARL J ,  SHEPARD JOSEPH F JR

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET(metal oxide semiconductor field effect transistor) and a method for manufacturing the MOSFET capable of eliminating the overlap of a gate dielectric and a source/drain region with high reliability.
SOLUTION: This method for manufacturing a MOSFET comprises the process of patterning a gate laminate constituted of a gate dielectric 20 arid a gate conductor 30 formed on a substrate 10, and the process of modifying the gate dielectric 20 beneath the gate dielectric 30 so that the gate dielectric 20 can have a central portion and a modified dielectric region 70 adjacent to the central portion. The modified dielectric region 70 has a lower dielectric constant than that of the gate dielectric 20, and the central portion is shorter than the gate conductor 30.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种MOSFET（金属氧化物半导体场效应晶体管）以及能够以高可靠性消除栅极电介质和源极/漏极区域的重叠的MOSFET的制造方法。 解决方案：用于制造MOSFET的方法包括对由栅极电介质20和形成在衬底10上的栅极导体30构成的栅极叠层的图案化以及在栅极电介质30下面改变栅极电介质20的工艺， 栅极电介质20可以具有与中心部分相邻的中心部分和改进的电介质区域70。 改性电介质区域70具有比栅极电介质20低的介电常数，并且中心部分比栅极导体30短。

公开(公告)号：JP2001085637A

公开(公告)日：2001-03-30

申请号：JP2000245911

申请日：2000-08-14

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： FURUKAWA TOSHIHARU ,  GRUENING ULRIKE ,  HORAK DAVID V ,  MANDELMAN JACK A ,  RADENS CARL J ,  RUPP THOMAS S

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain a vertical DRAM having a self-aligned word line conductor on the sidewall of a trench by forming a word line conductor having a sidewall aligned with the sidewall of the trench. SOLUTION: A pad nitride is removed selectively depending on the oxide 240 in an STI region 228. A screen oxide is then grown and array region p-well implantation is carried out and an N+ dopant is implanted in order to form a second diffusion region 210. Subsequently, source and drain implantation is carried out in a support region in order to form a diffusion region 288 and an oxide 242 is formed on the sidewalls 219, 233 of a word line conductor 218, 232 and on the sidewall of a support gate. Finally, a bit line conductor 244 of polysilicon is deposited for planarization. Since word line resistance is decreased, a DRAM device having improved performance can be obtained.

公开(公告)号：JP2000277708A

公开(公告)日：2000-10-06

申请号：JP2000073717

申请日：2000-03-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK A ,  NESBIT LARRY ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To prevent resistance of an embedded strap of a DRAM cell from changing by the overlapping manner of a deep trench and an active region. SOLUTION: This semiconductor device contains a semiconductor substrate. At least a pair of deep trenches are formed in the substrate. A collar is formed in at least a part of the sidewall of each of the deep trenches. The inside of each of the deep trenches is filled with a trench filler 44. An embedded strap 46 is formed over the whole of each of the deep trenches and covers the upper surfaces of the trench filler 44 and the collar. An insulating region is formed between a a pair of the deep trenches. A trench upper part dielectric region 52 formed in the deep trench, so as to overlap with the embedded strap 46 of each of the deep trenches.

公开(公告)号：JP2000058795A

公开(公告)日：2000-02-25

申请号：JP21248499

申请日：1999-07-27

Applicant: SIEMENS AG ,  IBM

Inventor： SHEN HUA ,  NUETZEL JOACHIM ,  RADENS CARL J ,  KOTECKI DAVID

IPC: H01G4/12 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To maintain an appropriate height of a lower part electrode while the surface region of the lower part electrode for a stacked capacity is improved, by forming a first electrode electrically combined to a conductive access path and then forming a second electrode on a dialectics layer formed on the first electrode. SOLUTION: A tapered surface 122 in a trench 116 is formed as a conical part in the trench 116. A lower part electrode (first electrode) 124 is formed on the upper surface comprising a side wall 118 (and the tapered surface 122) by deposition of a metal layer 126, for example, such noble metal as platinum (Pt). A high dielectric constant layer 134 is formed on the metal layer 126. The metal layer 126 forms a lower part electrode of a stacked capacitor. An upper part electrode (second electrode) 136 is formed by deposition of a conductive material above the high dielectric constant layer 134 in the trench 116. The upper part electrode 136 is prefered to be formed of platinum, while such a conductive material as iridium(Ir), for example, may be used.

公开(公告)号：JP2000012801A

公开(公告)日：2000-01-14

申请号：JP14714699

申请日：1999-05-26

Applicant: IBM ,  SIEMENS AG

Inventor： ECONOMIKOS LAERTIS ,  GRUENING ULRIKE ,  HO HERBERT L ,  RADENS CARL J ,  JAMMY RAGARAO ,  HOEPFNER JOACHIM ,  SHEN HUA

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned collar and a buried plate while forming a reliable node dielectrics on the collar without requiring a plurality of independent trench recesses for forming the buried plate and the collar. SOLUTION: Etching for a trench is made within a surface of a semiconductor substrate 10 and a dielectric material layer is formed on a side wall 12 of the trench. The dielectric material layer is partially eliminated to expose a lower base region of the upper part of the trench side wall 12. After that an oxide layer is made to grow on the upper part of the side wall 12. The dielectric layer is eliminated from a remaining part of the side wall 12 and a buried plate 17 is formed by doping. The dielectric layer includes the upper part of the collar and a node, (i,e, the trench wall at a portion of the buried plate 17) and is provided for the trench wall. An inner electrode 19 is formed at the inner part of the trench.

公开(公告)号：JP2003133317A

公开(公告)日：2003-05-09

申请号：JP2002193642

申请日：2002-07-02

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  RADENS CARL J ,  WANG LI-KONG ,  WONG KEITH KWONG HON

IPC: G03F7/40 ,  H01B13/00 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H05K3/02

Abstract: PROBLEM TO BE SOLVED: To provide a more simplified substitutional method of the conventional damascene approach. SOLUTION: The cloisonne approach includes a step of coating a semiconductor substrate with a photosensitive polymer, such as pyrrole having a silver salt, aniline, etc. A conductive polymer is exposed to a wet developing solution, by using standard photolithography and the resists developing method and only conductive polymer wires are left on a substrate by removing part of the exposed conductive polymer region. Then an insulating dielectric layer is adhered to the whole structure, and conductive polymer wires are produced by planarizing an insulator by the chemical mechanical polishing (CMP). Another embodiment of this invention includes a method and structure for a self- planarizing interconnecting material containing the conductive polymer. Consequently, the number of treating steps can be reduced, as compared with the conventional technology.

公开(公告)号：JP2002305287A

公开(公告)日：2002-10-18

申请号：JP2002016927

申请日：2002-01-25

Applicant: IBM

Inventor： MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal-oxide film semiconductor integrated circuit which contains a notched gate in a support device region, and to provide a method of forming the integrated circuit. SOLUTION: A gate stack 16 is formed on a substrate, a patterned mask 24 is formed on the gate stack, the stack gate is etched by using the mask, and rather than the entire part but a part of a gate conductor is removed. A gap-filling film 28 is formed on the whole face, and the gap-filling film is removed in such a way that the gap filling film is left between masked gate stacks in an array device region. A spacer is formed on the exposed sidewall of the masked gate stack, and the exposed gate conductor inside the array device region and inside the support device region is removed. An undercut is formed in the lower exposed part of the remaining gate conductor. The remaining gap filling film is removed from the masked protective gate stack inside the array device region.