公开(公告)号：EP2084738A4

公开(公告)日：2011-10-12

申请号：EP07844133

申请日：2007-10-11

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  YANG HAINING S ,  WONG KEITH KWONG HON ,  FAROOQ MUKTA G

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2047505A4

公开(公告)日：2011-10-05

申请号：EP07840384

申请日：2007-07-10

Applicant: IBM

Inventor： YANG CHIH-CHAO

IPC: H01L21/768 ,  H01L23/52

CPC classification number: H01L21/7682 ,  H01L21/76835

公开(公告)号：EP1920493A4

公开(公告)日：2011-05-04

申请号：EP06802645

申请日：2006-08-30

Applicant: IBM

Inventor： HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01H50/00 ,  H01P1/10

CPC classification number: H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

公开(公告)号：EP1941545A4

公开(公告)日：2011-03-30

申请号：EP06825349

申请日：2006-10-03

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  GAUDET SIMON ,  LAVOIE CHRISTIAN ,  PONOTH SHOM ,  SPOONER TERRY A

IPC: H01L23/58 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1869700A4

公开(公告)日：2010-12-15

申请号：EP06740771

申请日：2006-04-07

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1836726A4

公开(公告)日：2010-07-28

申请号：EP05852629

申请日：2005-12-02

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL J ,  STANDAERT THEODORUS E ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L21/4763

CPC classification number: H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2084711A4

公开(公告)日：2009-11-25

申请号：EP07843111

申请日：2007-09-25

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  YANG HAINING

IPC: G11C17/14 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2013080971A

公开(公告)日：2013-05-02

申请号：JP2013019016

申请日：2013-02-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： LAWRENCE CLEVENGER ,  TIMOTHY JOSEPH DALTON ,  HSU LOUIS LU-CHEN ,  RADENS CARL JOHN ,  VIDYA RAMACHANDRAN ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L27/04

CPC classification number: H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming semiconductor devices having wafer back-side capacitors.SOLUTION: A method includes the following steps of: preparing an SOI substrate having a buried insulating layer inserted between a front-side active silicon layer and a back-side bulk silicon layer; forming on the front side of the SOI substrate an integrated circuit including a buried contact plug extending from the front side of the SOI substrate while penetrating through the buried insulating layer; performing back-side etching process to form a trench in the bulk silicon layer and expose an end part of the buried contact plug to the back side surface of the buried insulating layer; and forming in a trench a capacitor including a first capacitor plate, a second capacitor plate, and a capacitor dielectric layer inserted between the first and second capacitor plates. The first capacitor plate is formed to contact with the exposed end part of the buried contact plug.

Abstract translation: 要解决的问题：提供一种形成具有晶片背面电容器的半导体器件的方法。 解决方案：一种方法包括以下步骤：制备插入在前侧活性硅层和后侧体硅层之间的埋入绝缘层的SOI衬底; 在SOI衬底的正面上形成集成电路，该集成电路包括从SOI衬底的前侧延伸穿过掩埋绝缘层的埋入式接触插塞; 执行背面蚀刻工艺以在体硅层中形成沟槽，并将埋入的接触插塞的端部暴露于掩埋绝缘层的背面; 以及在沟槽中形成包括插入在所述第一和第二电容器板之间的第一电容器板，第二电容器板和电容器电介质层的电容器。 第一电容器板形成为与埋入式接触插塞的暴露端部接触。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2007251155A

公开(公告)日：2007-09-27

申请号：JP2007039112

申请日：2007-02-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YANG CHIH-CHAO ,  HSU LOUIS LU-CHEN

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an interconnect structure having a barrier-redundancy constituent, and a method of forming the interconnect structure.
SOLUTION: A via diffusion barrier 30 exists on a portion of a conductive line 20. A conductive material 54 existing on a portion having no barrier 30 on the conductive line 20 provides an electrical path between a conductive line diffusion barrier 22 and the via diffusion barrier 30. Accordingly, an internal barrier-redundancy constituent is formed, using the conductive material 54, the conductive line diffusion barrier 22 and the via diffusion barrier 30. This electrical path to be provided by the barrier-redundancy constituent can avoid a sudden circuit open resulted from EM failure of the via bottom. Thus, after the EM failure is detected by a monitoring device, the barrier-redundancy constituent for providing a sufficient time for chip replacement or system operation adjustment is provided to the interconnect structure.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有阻挡冗余部件的互连结构以及形成互连结构的方法。 解决方案：通孔扩散阻挡层30存在于导电线20的一部分上。存在于导电线20上的不具有阻挡层30的部分上的导电材料54提供导电线扩散阻挡层22和 因此，使用导电材料54，导电线扩散阻挡层22和通孔扩散阻挡层30形成内部阻挡 - 冗余部件。由阻挡冗余部件提供的电路可以避免 由于通孔底部的EM故障导致突然断路。 因此，在通过监视装置检测到EM故障之后，向互连结构提供用于为芯片更换或系统操作调整提供足够时间的屏障冗余部件。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007158330A

公开(公告)日：2007-06-21

申请号：JP2006317786

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  LOUIS LU-CHEN HSU ,  YANG CHIH-CHAO ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/786

CPC classification number: H01L23/5256 ,  H01L21/268 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure including at least one e-fuse, and a manufacturing method which is easily integrated with standard semiconductor technologies, thus minimizing implementation costs. SOLUTION: A semiconductor structure includes at least one e-fuse embedded in a trench that is located in a semiconductor substrate (a bulk or semiconductor-on-insulator substrate). According to the present invention, the e-fuse is in electrical contact with a dopant region that is located in the semiconductor substrate. The present invention also provides a method of manufacturing the semiconductor structure in which the embedded e-fuse and trench isolation regions are formed almost at the same time. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供包括至少一个电熔丝的半导体结构和容易与标准半导体技术集成的制造方法，从而最小化实施成本。 解决方案：半导体结构包括嵌入在半导体衬底（主体或绝缘体上半导体衬底）上的沟槽中的至少一个电熔丝。 根据本发明，电熔丝与位于半导体衬底中的掺杂区电接触。 本发明还提供了一种制造半导体结构的方法，其中嵌入式电熔丝和沟槽隔离区几乎同时形成。 版权所有（C）2007，JPO＆INPIT