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    25.
    发明专利
    未知

    公开(公告)号：DE102005026899A1

    公开(公告)日：2006-12-14

    申请号：DE102005026899

    申请日：2005-06-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STRAEUSNIGG DIETMAR ,  RAINER BERND ,  WIESBAUER ANDREAS ,  GAGGL RICHARD ,  CLARA MARTIN ,  HERNANDEZ LUIS

    IPC: H03M1/66 ,  H03M1/06

    Abstract: A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.

    27.
    发明专利
    未知

    公开(公告)号：DE102004045709A1

    公开(公告)日：2006-04-06

    申请号：DE102004045709

    申请日：2004-09-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： CLARA MARTIN ,  KOLHAUPT KLAUS ,  WIESBAUER ANDREAS ,  DI GIANDOMENICO ANTONIO

    IPC: H03F3/45 ,  H03F1/34

    Abstract: An amplifier and method of setting the amplifier is presented. The amplifier is set by setting a mean value between voltage values at first and second outputs of the amplifier. The mean value is pulled towards a certain voltage potential. A circuit node is coupled to the first and to the second output. The circuit node is connected, via at least one resistor and a respective switch, to the certain voltage potential assigned to the respective resistor.

    28.
    发明专利
    未知

    公开(公告)号：DE50008004D1

    公开(公告)日：2004-11-04

    申请号：DE50008004

    申请日：2000-04-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WIESBAUER ANDREAS ,  WEINBERGER HUBERT ,  CLARA MARTIN ,  HAUPTMANN JOERG

    IPC: H03M3/04

    Abstract: A sigma-delta analog-to-digital converter array including two cascaded sigma-delta modulators, the two sigma-delta modulators being multi-bit sigma-delta modulators. The sigma-delta analog-to-digital converter array is preferably a third order device and supplies a digital output signal corresponding to a sigma-delta converter with 7-bit quantization. To this end, a second order sigma-delta modulator with 3-bit quantization and a first order sigma-delta modulator with 5-bit quantization may be used.

    29.
    发明专利
    未知

    公开(公告)号：DE10158244B4

    公开(公告)日：2004-02-12

    申请号：DE10158244

    申请日：2001-11-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： CLARA MARTIN ,  WIESBAUER ANDREAS

    IPC: H01L27/02 ,  H02H9/04 ,  H02M3/156 ,  H02H7/20

    Abstract: A high-voltage circuit (HVC) (100) is set up to apply an excess voltage (101) to supply circuit units. A low-voltage (LV) device (116) with a LV circuit (115) is set up to run LV circuit functions. Also, a source (114) of voltage protection sets up a protection voltage (113). A protective device (PD) (111) to protect the low-voltage (LV) device from damage through excess voltage on the high-voltage circuit (HVC) connects so that the PD connects in series between the HVC and the LV device. An Independent claim is also included for a device for protecting low-voltage devices working with a high-voltage circuit against damage through excess voltage on a high-voltage circuit.

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