公开(公告)号：DE59914245D1

公开(公告)日：2007-04-19

申请号：DE59914245

申请日：1999-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  LEHMANN VOLKER ,  STENGL REINHARD ,  WENDT HERMANN ,  LANGE GERRIT ,  BACHHOFER HARALD ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

IPC: H01L21/8242 ,  H01L27/108

Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

公开(公告)号：DE102004007697B3

公开(公告)日：2005-07-14

申请号：DE102004007697

申请日：2004-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OPPERMANN KLAUS-GUENTER ,  FRANOSCH MARTIN ,  MECKES ANDREAS

IPC: B81B7/00 ,  H01L21/50 ,  H03H3/08 ,  H01L21/48 ,  B81C1/00 ,  B81C3/00

Abstract: A process for etching a sacrificial layer (8), comprises preparing a system wafer (7), preparing a carrier wafer (9), arranging the carrier wafer on the system wafer so lid sections (3) are arranged on a frame structure (4), filling hollow chambers (6) between the two wafers, removing the carrier wafer after etching, and separating out the semiconductor chips. The etching agent has a predetermined concentration, calculated based on the volume of the sacrificial layer.

公开(公告)号：DE10353767A1

公开(公告)日：2005-06-30

申请号：DE10353767

申请日：2003-11-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  MECKES ANDREAS ,  OPPERMANN KLAUS-GUENTER

IPC: B81B7/00 ,  B81C1/00

公开(公告)号：DE10316776B4

公开(公告)日：2005-03-17

申请号：DE10316776

申请日：2003-04-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  MECKES ANDREAS ,  OPPERMANN KLAUS-GUENTER

IPC: B81B7/00 ,  H03H3/007 ,  H03H9/02 ,  H01L21/56 ,  B81B3/00 ,  B81C1/00 ,  H03H3/08 ,  H03H9/10

Abstract: A protected component is contained in substrate (100) and the method includes deposition of first cover layer (110) onto substrate, at least over region (104) containing component and forming at least one aperture (112a) in first cover layer, exposing substrate region, containing component. The aperture is filled with appropriate material (118). Second layer (150) is deposited onto first cover layer with filled aperture. In second cover layer is formed at least one second aperture (152) to expose region of filling material, which is then removed and aperture in second cover layer is closed.

公开(公告)号：DE10316776A1

公开(公告)日：2004-11-11

申请号：DE10316776

申请日：2003-04-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  MECKES ANDREAS ,  OPPERMANN KLAUS-GUENTER

IPC: B81B7/00 ,  H03H3/007 ,  H03H9/02 ,  H01L21/56 ,  B81B3/00 ,  B81C1/00 ,  H03H3/08 ,  H03H9/10

Abstract: A protected component is contained in substrate (100) and the method includes deposition of first cover layer (110) onto substrate, at least over region (104) containing component and forming at least one aperture (112a) in first cover layer, exposing substrate region, containing component. The aperture is filled with appropriate material (118). Second layer (150) is deposited onto first cover layer with filled aperture. In second cover layer is formed at least one second aperture (152) to expose region of filling material, which is then removed and aperture in second cover layer is closed.

公开(公告)号：DE10316777A1

公开(公告)日：2004-11-04

申请号：DE10316777

申请日：2003-04-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OPPERMANN KLAUS-GUENTER ,  FRANOSCH MARTIN ,  MECKES ANDREAS

IPC: H03H3/02 ,  H03H3/08 ,  H03H9/10 ,  H01L21/56 ,  B81B3/00 ,  B81C1/00 ,  H03H3/007

Abstract: Sacrificial structure (108) is produced on the substrate (100). A first section (110) of the sacrificial structure covers a first region (104) of the substrate which includes the component. A second section (112) extends from the first region into a second region (106) of the substrate without components. A first covering layer (114) is deposited, to surround the sacrificial structure, such that the second section (112) is left bare. The sacrificial layer is removed. The structure formed by removing the sacrificial layer is sealed.

公开(公告)号：DE10206919A1

公开(公告)日：2003-08-28

申请号：DE10206919

申请日：2002-02-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MECKES ANDREAS ,  AIGNER ROBERT ,  OPPERMANN KLAUS GUENTER ,  FRANOSCH MARTIN ,  STRASSER MARC

IPC: B81B7/00 ,  H03H9/10 ,  B81C3/00 ,  H01L21/52

Abstract: Production of a cover for a region of a substrate (10) comprises forming a frame structure (18) in the region of the substrate, and applying a lid structure (20) on the frame structure so that the region between the lid structure and the substrate is covered. An Independent claim is also included for a process for the production of a housed component comprising preparing a substrate with a component, forming a cover as above for a region of the substrate, and completing the housed component by applying a material which does not penetrate the region between the lid structure and the substrate.

公开(公告)号：DE59707274D1

公开(公告)日：2002-06-20

申请号：DE59707274

申请日：1997-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUSTIG DR ,  SCHAEFER DR ,  FRANOSCH MARTIN

IPC: H01L21/8238 ,  H01L21/8256 ,  H01L21/84 ,  H01L21/86 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

Abstract: An integrated complementary metal oxide semiconductor (CMOS) circuit structure has semiconductor islands (6) which have Si1-xGex and strained silicon layers (4, 5) with the same lattice constants and which are formed on an insulating layer (2) on a support (1), p-channel and n-channel MOS transistors being provided in respective islands. Also claimed is the production of an integrated CMOS circuit structure, in which: (a) the silicon layer (3) of a silicon-on-insulator (SOI) substrate (1, 2, 3) is structured to form islands and partially expose the insulating layer (2) surface; (b) a Si1-xGex layer (4) and a strained silicon layer (5) are produced on the structured silicon layer (3) to form semiconductor islands (6); (c) the thickness of the Si1-xGex layer (4) is chosen in accordance with that of the structured silicon layer (3) to achieve lattice constant matching; and (d) n-channel and/or p-channel transistors are formed in the semiconductor islands (6).

公开(公告)号：DE59705585D1

公开(公告)日：2002-01-10

申请号：DE59705585

申请日：1997-09-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUSTIG BERNHARD ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

Abstract: PCT No. PCT/DE97/01933 Sec. 371 Date Jun. 4, 1999 Sec. 102(e) Date Jun. 4, 1999 PCT Filed Sep. 3, 1996 PCT Pub. No. WO98/13865 PCT Pub. Date Apr. 2, 1998In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep dopant profiles. The LDD profile is preferably produced by etching and in situ doped selective epitaxy.

公开(公告)号：DE59705303D1

公开(公告)日：2001-12-13

申请号：DE59705303

申请日：1997-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER HERBERT ,  FRANOSCH MARTIN ,  STENGL REINHARD ,  LEHMANN VOLKER ,  REISINGER HANS ,  WENDT HERMANN

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205

Abstract: PCT No. PCT/DE97/01408 Sec. 371 Date Feb. 9, 1999 Sec. 102(e) Date Feb. 9, 1999 PCT Filed Jul. 3, 1997 PCT Pub. No. WO98/07184 PCT Pub. Date Feb. 19, 1998For manufacturing a capacitor that is essentially suited for DRAM arrangements, column structures that form an electrode of the capacitor are etched upon employment of a statistical mask that is produced without lithographic steps by nucleus formation of Si/Ge and subsequent selective epitaxy. Structure sizes below 100 nm can be realized in the statistical mask. Surface enlargement factors up to 60 are thus achieved.