公开(公告)号：DE59712073D1

公开(公告)日：2004-12-16

申请号：DE59712073

申请日：1997-07-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ELBEL NORBERT ,  GABRIC ZVONIMIR ,  NEUREITHER BERNHARD

IPC: H01L21/76 ,  H01L21/74 ,  H01L21/762

Abstract: A laterally insulated buried zone of increased conductivity is fabricated in a semiconductor substrate. First, a reference layer is formed on a substrate with a buried zone of increased conductivity. Then the reference layer is patterned. A trench is produced in the substrate, and the insulation material used for filling the trench is applied to the structure thus produced. A planar surface is thereby formed in that the growth rate in the trench is faster than the growth rate on the reference layer adjacent the trench. Here, the reference layer is chosen such that the growth rate of the insulation material on the reference layer is at least a factor of two less than the growth rate of the insulation material on the surface of the trench which is to covered. This trench surface to be covered will usually be composed of substrate material. However, intermediate layers may also be provided.

公开(公告)号：DE59708003D1

公开(公告)日：2002-09-26

申请号：DE59708003

申请日：1997-06-27

Applicant: INFINEON TECHNOLOGIES AG ,  FRAUNHOFER GES FORSCHUNG

Inventor： GABRIC ZVONIMIR ,  SPINDLER DR ,  GRASSL THOMAS

IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: Production of an insulation layer, functioning as an inter-metal dielectric (IMD), involves: (a) covering a substrate surface (2) with a first insulating layer (3) and then a metal (preferably aluminium) layer; (b) photo-structuring the metal layer to form circuit lines (4) which are then covered with a second insulating layer (7) on their surfaces and side faces (6); (c) removing the second insulating layer material (7) from the first insulating layer regions (3) between the circuit lines (4); and (d) depositing a third insulating layer (8) on the resulting structure by ozone-activated CVD with a growth rate which is greater on the first insulating layer material (3) than on the second insulating layer material (7). Preferably, the first insulating layer material (3) is phosphosilicate glass, borophosphosilicate glass or undoped silicate glass and the second insulating layer material (7) is titanium nitride.

公开(公告)号：AT222664T

公开(公告)日：2002-09-15

申请号：AT97110594

申请日：1997-06-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GABRIC ZVONIMIR ,  SPINDLER OSWALD DR ,  GRASSL THOMAS

IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: Production of an insulation layer, functioning as an inter-metal dielectric (IMD), involves: (a) covering a substrate surface (2) with a first insulating layer (3) and then a metal (preferably aluminium) layer; (b) photo-structuring the metal layer to form circuit lines (4) which are then covered with a second insulating layer (7) on their surfaces and side faces (6); (c) removing the second insulating layer material (7) from the first insulating layer regions (3) between the circuit lines (4); and (d) depositing a third insulating layer (8) on the resulting structure by ozone-activated CVD with a growth rate which is greater on the first insulating layer material (3) than on the second insulating layer material (7). Preferably, the first insulating layer material (3) is phosphosilicate glass, borophosphosilicate glass or undoped silicate glass and the second insulating layer material (7) is titanium nitride.

公开(公告)号：DE102005039323A1

公开(公告)日：2007-02-22

申请号：DE102005039323

申请日：2005-08-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GABRIC ZVONIMIR ,  STICH ANDREAS ,  PAMLER WERNER ,  SCHINDLER GUENTHER

IPC: H01L23/522 ,  H01L21/768

Abstract: A conduction path arrangement has a substrate (1,2), at least two conduction paths (4), formed adjacent to one another over the substrate, and a cavity which is formed at least between the conduction paths (4), and a dielectric covering layer (5) covering the conduction paths and enclosing the cavity. The support paths (TB) between the substrate (1,2) and the conduction paths (4) are designed to support the conduction paths, in which on the contact surface, a width (B1) of the conduction paths is greater than a width (B2) of the support paths (TB). An independent claim is included for a method for fabrication a conduction path arrangement.

公开(公告)号：DE10341544B4

公开(公告)日：2005-10-13

申请号：DE10341544

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  PAMLER WERNER ,  GABRIC ZVONIMIR ,  UNGER EUGEN

IPC: H01L21/768 ,  H01L23/522

公开(公告)号：DE10341544A1

公开(公告)日：2005-04-07

申请号：DE10341544

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  PAMLER WERNER ,  GABRIC ZVONIMIR ,  UNGER EUGEN

IPC: H01L21/768 ,  H01L23/522

Abstract: Strip conductor arrangement comprises a strip conductor arranged in a substrate (102), additional strip conductors arranged next to each other over the substrate, a covering layer completely covering the additional strip conductors, a hollow chamber (112) arranged between the additional strip conductors and extending laterally to the additional strip conductors and to the covering layer, wall layers (100) delimiting the hollow chamber laterally to the additional strip conductors and to the covering layer, plugs (111) arranged over the hollow chamber and between the wall layers, a first layer arranged between the substrate and the additional strip conductors and the wall layers, and a second layer arranged on the plugs and the wall layers in the covering layer. An independent claim is also included for a process for the production of the strip conductor arrangement.

公开(公告)号：AT282247T

公开(公告)日：2004-11-15

申请号：AT97935455

申请日：1997-07-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ELBEL NORBERT ,  GABRIC ZVONIMIR ,  NEUREITHER BERNHARD

IPC: H01L21/76 ,  H01L21/74 ,  H01L21/762

Abstract: A laterally insulated buried zone of increased conductivity is fabricated in a semiconductor substrate. First, a reference layer is formed on a substrate with a buried zone of increased conductivity. Then the reference layer is patterned. A trench is produced in the substrate, and the insulation material used for filling the trench is applied to the structure thus produced. A planar surface is thereby formed in that the growth rate in the trench is faster than the growth rate on the reference layer adjacent the trench. Here, the reference layer is chosen such that the growth rate of the insulation material on the reference layer is at least a factor of two less than the growth rate of the insulation material on the surface of the trench which is to covered. This trench surface to be covered will usually be composed of substrate material. However, intermediate layers may also be provided.

公开(公告)号：DE10228344A1

公开(公告)日：2004-01-15

申请号：DE10228344

申请日：2002-06-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHWARZL SIEGFRIED ,  PAMLER WERNER ,  GABRIC ZVONIMIR

IPC: H01L21/768 ,  H01L23/522 ,  B81B1/00

Abstract: A method referred to as a "cellular damascene method" utilizes a multiplicity of regularly arranged closed cavities referred to as "cells", which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.

公开(公告)号：DE10207130A1

公开(公告)日：2003-09-11

申请号：DE10207130

申请日：2002-02-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINRICH VOLKER ,  PAMLER WERNER ,  GABRIC ZVONIMIR

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L21/283 ,  H01L21/768

Abstract: A method for improving the adhesion between a noble metal layer and an insulation layer includes configuring a silicon layer between the noble metal layer and the insulation layer. The silicon layer is siliconized and oxidized by a thermal treatment in an oxidative environment, resulting in an oxidized silicide layer with high intermixing of the noble metal and the formed oxide. The relatively large inner surface achieved as a result improves the adhesion between the noble metal layer and the insulation layer.

公开(公告)号：DE10125019A1

公开(公告)日：2002-12-05

申请号：DE10125019

申请日：2001-05-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PAMLER WERNER ,  ENGELHARDT MANFRED ,  GABRIC ZVONIMIR

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/314

Abstract: The invention relates to a hollow structure (100) in an integrated circuit, comprising a substrate (101) having a surface (102), conductor tracks (103) which are adjacently arranged on said surface in such a way that they form intermediate spaces (104) thereinbetween, a first layer (105) consisting of a first insulation material which is arranged over each conductor track (103), and a second layer (106) covering the intermediate spaces (104), consisting of a second insulation material which is deposited only on the first insulation material.