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    21.
    发明专利
    未知

    公开(公告)号：DE102004033148B4

    公开(公告)日：2007-02-01

    申请号：DE102004033148

    申请日：2004-07-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ILICALI GUERKAN ,  LUYKEN JOHANNES R ,  ROESNER WOLFGANG

    IPC: H01L21/336 ,  H01L29/78

    Abstract: A process for producing a layer arrangement, which layer arrangement allows a dual gate field-effect transistor to be formed. In this process, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate. A first semiconductor layer is formed on the sacrificial layer, and a first electrically insulating layer is formed on the first semiconductor layer. An electrically conductive layer is formed on the first electrically insulating layer, which electrically conductive layer is laterally patterned. The first electrically insulating layer, the sacrificial layer and the first semiconductor layer are jointly laterally patterned using the laterally patterned electrically conductive layer as a mask. Furthermore, a semiconductor structure is formed adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer. A substrate is secured over the patterned electrically conductive layer, and material of the auxiliary substrate is removed, so that the sacrificial layer is uncovered. Furthermore, the sacrificial layer is selectively removed, so as to form a trench, and a second electrically insulating layer is formed in the trench, then an electrically conductive structure is formed on this second electrically insulating layer.

    23.
    发明专利
    未知

    公开(公告)号：DE59813243D1

    公开(公告)日：2006-01-05

    申请号：DE59813243

    申请日：1998-09-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RISCH LOTHAR ,  ROESNER WOLFGANG ,  RAMCKE TIES ,  JACOBS HERMANN

    IPC: G11C17/10 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/112

    Abstract: Resistors are connected between word lines and bit lines running transversely with respect thereto. The resistors have a higher resistance than the word lines and the bit lines. The bit lines are each connected to a sense amplifier which regulates the potential on the respective bit line to a reference potential and at which an output signal can be picked off. If one of the word lines is selected and all the other word lines are put at reference potential, then the resistance of the resistor, which is assigned to an information item, can be read from the output signal.

    24.
    发明专利
    未知

    公开(公告)号：DE50007390D1

    公开(公告)日：2004-09-16

    申请号：DE50007390

    申请日：2000-05-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  RISCH LOTHAR

    IPC: H01L29/417 ,  H01L21/20 ,  H01L21/336 ,  H01L29/786

    Abstract: A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.

    Single-crystal silicon-on-insulator field effect transistor production, includes ion implantation to produce localized defects, and tempering to form oxide clusters
    25.
    发明专利
    Single-crystal silicon-on-insulator field effect transistor production, includes ion implantation to produce localized defects, and tempering to form oxide clusters 未知

    公开(公告)号：DE10250840A1

    公开(公告)日：2004-05-19

    申请号：DE10250840

    申请日：2002-10-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOFMANN FRANZ ,  HARTWICH JESSICA ,  ROESNER WOLFGANG ,  DREESKORNFELD LARS ,  LYKEN HANNES ,  LANDGRAF ERHARD

    IPC: H01L21/336 ,  H01L21/84 ,  H01L29/786

    Abstract: The silicon-on-insulator (SOI) substrate (10) is prepared. A trenched oxide layer (BOX) is embedded between a single-crystal silicon layer (14) and a substrate (12). An auxiliary oxide layer (16) is formed at least locally, on a surface of the silicon layer (14) which lies opposite the BOX. A polysilicon layer (18) is applied on a surface of the auxiliary oxide layer (16) facing the silicon layer (14). A gate region window (24) is etched in the polysilicon layer such that the surface of the auxiliary oxide layer is laid bare in the gate window. A protective layer (28) is applied on the bare surface (26). Defects are produced by ion implantation in an ion implantation zone (30) of the auxiliary oxide layer which is not covered by the protective layer. The SOI substrate (10) with the auxiliary oxide-, the polysilicon- and the protective layer is subjected to tempering, so that the auxiliary oxide layer at least locally in the implantation region, is broken up into oxide clusters. The protective layer is removed. The auxiliary oxide layer is removed from the gate window. A gate oxide layer is constructed on the surface of the silicon layer at least locally in the gate region window. The gate electrode (36) is applied to the gate oxide layer. Source and drain connections are applied to the polysilicon layer in the implantation zone.

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