公开(公告)号：DE10244400A1

公开(公告)日：2004-04-01

申请号：DE10244400

申请日：2002-09-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER ANDRE ,  PFEIFFER JOHANN ,  SZCZYPINSKI KASIMIERZ ,  SCHNABEL JOACHIM

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4063

Abstract: A circuit arrangement (1) having at least one terminal (3b) to which a clock/data signal (/CLK,/CLKt) can be applied. The circuit arrangement in addition has a clock-signal-ascertaining-device (2) for ascertaining whether a clock signal (/CLK,/CLKt) is present at the terminal (3b). An Independent claim is included for a semiconductor component i.e. a DDR (double data rate) component, especially a memory component, such as a DRAM..

公开(公告)号：DE50100988D1

公开(公告)日：2003-12-24

申请号：DE50100988

申请日：2001-06-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRASS ECKHARD ,  LE THOAI-THAI ,  LINDOLF JUERGEN ,  SCHNABEL JOACHIM

IPC: G11C11/409 ,  G11C5/14 ,  G11C7/06 ,  G11C7/22 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  H03K19/0175

Abstract: The circuit generates a control voltage derived from a reference current per differential amplifier acting as a receiver to set the correct operating point. Switching elements for each receiver in a line carrying a current for generating the control voltage are permanently closed in working mode by a trigger signal (EN) to continuously deliver the current and are closed periodically or at discrete times in standby mode by a refresh signal. The circuit generates a control voltage derived from a reference current (IREF) for each differential amplifier (6,7) functioning as a receiver to set the correct operating point. It has switching elements (10-12) for each receiver in a line (13) carrying a current for generating the control voltage and that are permanently closed in working mode by a trigger signal (EN) to continuously deliver the current and that are closed periodically or at discrete times in standby mode by a refresh signal (SRF). Independent claims are also included for the following: a DRAM memory.

公开(公告)号：DE10219783A1

公开(公告)日：2003-11-20

申请号：DE10219783

申请日：2002-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAUSMANN MICHAEL ,  SCHNABEL JOACHIM

IPC: H02M3/07

Abstract: A method for increasing the external supply voltage (Vext) of an integrated circuit, using a two-stage charge pump (A,B) to transform the external supply voltage (Vext) on to a higher internal working voltage (Vpp). Two two-stage pumps (A,B) work in parallel in one multi-phase drive, where in a cyclic sequence the two pumps (A,B) work on a common first stage. An Independent claim is given for an integrated circuit.

公开(公告)号：DE10219371A1

公开(公告)日：2003-11-20

申请号：DE10219371

申请日：2002-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAUSMANN MICHAEL ,  SCHNABEL JOACHIM

IPC: H02M1/08 ,  H02M3/07

Abstract: Signal generating device (10) has signal outputs (D1...Dn) and a signal frequency setting input (12) for adjusting the frequency (F) and is designed such that a periodic signal (Sx(t)) can be outputted via the signal output (Dx), and all signals (S1(t)...SN(t)) have the same adjustable frequency (f). The signal (Sx(t)) is less than or equal to (x) which is less than or equal (N) and is valid for the relationship (Sx(t)=S1(t-(x-1).delta tx-kx/(2f)). The delay time (delta Tx) of the signal (Sx(t)) relative to the relationship (Sx-1(t)) and the relationship (kx epsilon (0.1)). The delay time (delta Tx) is dependent on the frequency (f). An Independent claim is given for an integrated circuit comprising a signal generating device.

公开(公告)号：DE10157865A1

公开(公告)日：2003-06-26

申请号：DE10157865

申请日：2001-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  KLEHN BERND ,  SCHNABEL JOACHIM

IPC: G11C5/14 ,  H02M3/07 ,  H01L23/58

Abstract: A programmable voltage pump (1) has a trim input (TRIM) for adjusting a desired output voltage (VNEG) as well as an output (OUT) where the output voltage is emitted. At the output (OUT) of the voltage pump there is a particularly easy means for generating an overflow level at the output of the voltage pump i.e. there is a switch (2) at the output that gives the option of earthing the output.

公开(公告)号：DE10101997C2

公开(公告)日：2003-05-28

申请号：DE10101997

申请日：2001-01-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAFFROTH THILO ,  SCHNABEL JOACHIM

IPC: G05F1/46 ,  H01L21/66 ,  H01L23/58

公开(公告)号：DE10137373A1

公开(公告)日：2003-02-20

申请号：DE10137373

申请日：2001-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL JOACHIM ,  KLEHN BERND ,  ZUCKERSTAETTER ANDREA ,  KLEIN RALF

IPC: G11C7/10 ,  H03K3/027 ,  G01R31/3177

Abstract: A control signal and an activation signal are applied to a control signal connection unit (100) and an activation connection unit (101), respectively. A hold signal generated in response to the activation signal, is combined with the control signal to obtain a modified control signal. An Independent claim is also included for control signal generating device.

公开(公告)号：DE10026275A1

公开(公告)日：2001-12-13

申请号：DE10026275

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAS ECKHARD ,  SCHAFFROTH THILO ,  SCHNABEL JOACHIM ,  SCHNEIDER HELMUT

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/12 ,  G11C29/26 ,  H01L27/10 ,  G11C29/00

Abstract: A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.

公开(公告)号：DE102006047410A1

公开(公告)日：2008-04-10

申请号：DE102006047410

申请日：2006-10-06

Applicant: QIMONDA AG ,  INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  SCHNABEL JOACHIM

IPC: H02M3/07

Abstract: The circuit (1) has a charge pump (100) switched on and off by a switching unit. Another switching unit is connected with an output of the pump at one end and with a supply potential at another end, where the switching units are n-or p-channel field effect transistors. A comparator (103) compares two potentials so that a signal is produced for controlling control inputs of the latter unit. An electrical circuit is supplied with an output voltage (Vneg) output by the pump, where the voltage is absolutely larger than a value of a supply voltage supplied by a circuit arrangement. An independent claim is also included for a method for operating a comparator for providing output signals.

公开(公告)号：DE10214101B4

公开(公告)日：2007-05-31

申请号：DE10214101

申请日：2002-03-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL JOACHIM ,  SCHAEFER ANDRE

IPC: G11C11/406 ,  G11C7/04 ,  G11C11/4076 ,  H03K3/0231 ,  H03K3/0232 ,  H03L7/00

Abstract: The device has a capacitor, a differential current source for providing a capacitor charging current with temperature dependent and temperature independent current sources connected together so the current level of the capacitor charging current is proportional to the difference between the temperature dependent and temperature independent currents. A comparator outputs a refresh signal if the capacitor voltage exceeds a reference voltage. The device has a capacitor (C), a differential current source (14) for providing a capacitor charging current for charging the capacitor with temperature dependent and temperature independent current sources that are connected together so that the current level of the capacitor charging current is proportional to the difference between the temperature dependent and temperature independent currents. A comparator (12) outputs a refresh signal if the capacitor voltage (VC) exceeds a reference voltage (VREF). AN Independent claim is also included for the following: an arrangement for implementing the inventive method of producing a refresh signal for a memory cell of a semiconducting memory device, preferably a DRAM memory.