公开(公告)号：DE10211932A1

公开(公告)日：2003-10-09

申请号：DE10211932

申请日：2002-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS

IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50

Abstract: A circuit arrangement includes a bit line ( 10 ), a reference bit line ( 12 ), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor ( 20, 22 ) and a p-channel field-effect transistor ( 30, 32 ), and also, at the respective source terminals, two voltage sources ( 40, 42 ), of which the voltage source ( 40 ) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source ( 42 ) linked to the p-channel field-effect transistors ( 30, 32 ) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell ( 4 ) on the bit line ( 10 ) if the threshold voltages (U TH1 , U TH2 ) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell ( 4 ).

公开(公告)号：DE10149199A1

公开(公告)日：2003-04-24

申请号：DE10149199

申请日：2001-10-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  SCHLOESSER TILL

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108

公开(公告)号：DE10137830A1

公开(公告)日：2003-02-27

申请号：DE10137830

申请日：2001-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  HECHT THOMAS ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

Abstract: A structure on a layer surface of the semiconductor wafer comprises at least one first surface (8,9) area reflecting electromagnetic radiation and at least one second substantially non-reflecting surface area (10,11,12). A transparent insulating layer (13) and a light-sensitive layer are produced on said layer surface. Electromagnetic radiation is directed at the light-sensitive layer at an incident angle &thetas; and the structure of the layer surface is imaged onto the light-sensitive layer with a lateral replacement.

公开(公告)号：DE10143936A1

公开(公告)日：2003-01-09

申请号：DE10143936

申请日：2001-09-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  LUETZEN JOERN ,  GOLDBACH MATTHIAS ,  BREUER STEFFEN ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/12 ,  H01L21/84 ,  H01L21/336

Abstract: Production of a layer stack made from a silicon oxide layer and a monocrystalline silicon layer on a substrate comprises: forming mesopores in the surface region of substrate; oxidizing the surface to form silicon oxide and bar regions; exposing the bar regions facing away from the substrate; and selectively epitaxially growing the silicon on exposed bar regions opposite the silicon oxide regions. Production of a layer stack made from a silicon oxide layer (11) and a monocrystalline silicon layer (12) on a substrate (2) comprises: forming mesopores (10) in the surface region (3) of the substrate; oxidizing the surface to form silicon oxide and bar regions (22) made from single crystalline silicon which remain between neighboring mesopores; exposing the bar regions facing away from the substrate; and selectively epitaxially growing the silicon on the exposed bar regions opposite the silicon oxide regions. Independent claims are also included for the following: (a) a vertical transistor; and (b) a storage cell. Preferred Features: The process further comprises heat treating to oxidize the silicon bar regions. The bar regions have a diameter of 5-15 nm. The bar regions are exposed by wet chemical etching. The silicon oxide layer is 10-50 nm thick.

公开(公告)号：DE10133688A1

公开(公告)日：2002-09-26

申请号：DE10133688

申请日：2001-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  FRANOSCH MARTIN

IPC: H01L21/02 ,  H01L21/3063 ,  H01L21/8242

Abstract: Production of the lower capacitor electrode of a trench capacitor comprises preparing a semiconductor substrate (1) with a trench (5) in a first main surface (2) of a substrate and a flat ohmic contact on the side of the trench facing the first main surface; forming an electrical connection on the ohmic contact; and electrochemically etching mesopores on an exposed surface region of the substrate electrically connected to the ohmic contact. The ohmic contact acts as an anode. Preferred Features: The step of preparing the substrate comprises forming an SOI substrate, forming the ohmic contact, and etching the trench capacitor through a p-doped silicon layer and a SiO2 layer into an n-doped substrate.

公开(公告)号：DE10108290A1

公开(公告)日：2002-09-12

申请号：DE10108290

申请日：2001-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  GOLDBACH MATTHIAS

IPC: H01L27/108 ,  H01L21/8242

Abstract: The invention relates to an electrode arrangement for charge storage with an external trench electrode (202; 406), embodied along the wall of a trench provided in a substrate (401) and electrically insulated on both sides in the trench by a first and a second dielectric (104; 405, 409); an internal trench electrode (201; 410), serving as counter-electrode to the external trench electrode (201; 406) and insulated by the second dielectric (104; 409) and a substrate electrode (201; 403), which is insulated by the first dielectric (104; 405) outside the trench, which serves as counter-electrode to the external trench electrode (202; 406) and is connected to the internal trench electrode (201; 410) in the upper trench region.

公开(公告)号：DE10055712A1

公开(公告)日：2002-05-23

申请号：DE10055712

申请日：2000-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  SCHUMANN DIRK

IPC: C25F3/12 ,  H01L21/3063 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L29/92

Abstract: Production of trench capacitors in a p-doped silicon layer comprises: (i) preparing a p-doped silicon layer having a prescribed resistivity; (ii) producing starting seeds on the front side of the silicon layer; (iii) applying an electrolyte to the front side of the silicon layer; (iv) applying an electrical voltage between the rear side of the silicon layer and the electrolyte so that an electric current with a given current density flows in the layer and trenches are produced; (v) forming a first electrode (2-24) in the trench; (vi) applying a capacitor dielectric (2-26) to the first electrode; and (vii) producing as second electrode (2-28) in the trench (2-22). Preferred Features: The p-doped silicon layer is a silicon wafer or part of a p-doped silicon wafer or lies on a p-doped silicon wafer. The p-doped silicon layer has a resistivity of less than 2 ohm.cm, preferably 0.3 ohm.cm.

公开(公告)号：DE102004027356B4

公开(公告)日：2007-08-16

申请号：DE102004027356

申请日：2004-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/088

公开(公告)号：DE102005024855A8

公开(公告)日：2007-03-08

申请号：DE102005024855

申请日：2005-05-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKSCHIK STEFAN ,  AVELLAN ALEJANDRO ,  SCHROEDER UWE ,  ORTH ANDREAS ,  GOLDBACH MATTHIAS ,  STORBECK OLAF ,  STADTMUELLER MICHAEL ,  HECHT THOMAS

IPC: H01L21/8242

Abstract: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

公开(公告)号：DE10321466B4

公开(公告)日：2007-01-25

申请号：DE10321466

申请日：2003-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  MANGER DIRK ,  GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SLESAZECK STEFAN

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/94

Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a "buried" collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.