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    23.
    发明专利
    未知

    公开(公告)号：FR2875352B1

    公开(公告)日：2007-05-11

    申请号：FR0409650

    申请日：2004-09-10

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  CANDELIER PHILIPPE ,  FOURNEL RICHARD

    IPC: H03M13/05 ,  G06F11/10 ,  H03M13/09 ,  H03M13/19 ,  H03M13/35 ,  H03M13/37

    Abstract: A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

    ARCHITECTURE DE MEMOIRE A LIGNES D'ECRITURE SEGMENTEES
    24.
    发明专利
    ARCHITECTURE DE MEMOIRE A LIGNES D'ECRITURE SEGMENTEES 未知

    公开(公告)号：FR2871921A1

    公开(公告)日：2005-12-23

    申请号：FR0406532

    申请日：2004-06-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： DRAY CYRILLE ,  BARASINSKI SEBASTIEN ,  LASSEUGUETTE JEAN ,  FREY CHRISTOPHE ,  FOURNEL RICHARD

    IPC: G11C7/18 ,  G11C8/10 ,  G11C11/16

    Abstract: L'invention concerne un dispositif de mémoire, comprenant au moins une ligne d'écriture segmentée (10) formée d'au moins un segment d'écriture, dotée de moyens de programmation (90), lesdits moyens de programmation (90) étant commandés par des moyens d'adressage de ligne (190) en mode écriture dudit dispositif de mémoire, pour programmer au moins une cellule mémoire (30) couplée à ladite ligne d'écriture segmentée, une ligne de bit de lecture (150) étant reliée à un circuit de lecture (110) pour lire le contenu de ladite cellule en mode lecture dudit dispositif de mémoire, caractérisé en ce que ladite ligne de bit de lecture coopère en mode écriture avec lesdits moyens d'adressage de ligne pour commander lesdits moyens de programmation de ladite ligne d'écriture segmentée.

    Memory cell which is electrically programmable by degrading at least locally the gate oxide layer of a MOS transistor so to obtain a current variation in reading operation
    26.
    发明专利
    Memory cell which is electrically programmable by degrading at least locally the gate oxide layer of a MOS transistor so to obtain a current variation in reading operation 未知

    公开(公告)号：FR2846464A1

    公开(公告)日：2004-04-30

    申请号：FR0213497

    申请日：2002-10-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE

    IPC: G11C11/56 ,  G11C17/14 ,  G11C17/08 ,  G11C17/18 ,  H01L27/115

    Abstract: The memory cell or point memory which is of electrically programmable read-only type comprises a MOS transistor with the gate oxide layer (14) and the gate (G) which is electrically connected. In programming operation the gate oxide layer (14) is degraded at least locally at point Z so to obtain in the reading operations a variation of current (Id) delivered by the transistor. The MOS transistor is a transistor with thin gate oxide layer (GO1), whose thickness is substantially equal to 2.5 nm. The gate oxide layer (14) is degraded as a function of used programming voltages. The degradation of the gate oxide layer is implemented in the full length of transistor channel (12), or in the vicinity of at least one electrode, source (S) and drain (D), in particular the drain electrode. A method (claimed) for programming the memory cell (claimed) consists of applying the programming voltages to the transistor electrodes which cause an irreversible degradation of the gate oxide layer of the transistor so that the read current (Id) is varied. In the course of programming the gate voltage is equal to at least 1.2 V, the voltage between the source and the drain is equal to about 3 V, and the bulk voltage is negative and qual to about -1 V. A method (claimed) for reading the memory cell consists of applying between the drain and the source a voltage in the range from 0.1 V to 1.2 V. An integrated circuit (claimed) comprises a central part with MOS transistors having the thin gate oxide layer (GO1) and a peripheral part with MOS transistors having a thicker gate oxide layer (GO2). The central part comprises a flat memory comprising memory cells with the MOS transistors having the thin gate oxide layer. In the write operation the programming voltages are applied to cause the degradation of the gate oxide layer of the selected transistor. A higher programming voltage is applied either to the drain or to the source of the memory cell so to cause degradations in the respective zones of the gate oxide layer. Each memory cell is also associated with another transistor allowing an adjustment of the source voltage of non-selected transistors. The thickness of the thicker gate oxide layer is substantially equal to 7 nm. The lower and the higher supply voltages are about 1.2 V and 3.3 V, respectively.

    Method for putting in waiting mode a component and associated integrated circuit
    28.
    发明专利
    Method for putting in waiting mode a component and associated integrated circuit 未知

    公开(公告)号：FR2838256A1

    公开(公告)日：2003-10-10

    申请号：FR0204303

    申请日：2002-04-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  LASSEUGUETTE JEAN ,  SCHOELLKOPF JEAN PIERRE

    IPC: H03K19/00 ,  H03K3/012

    Abstract: The component (C) comprises several complementary MOS transistors implemented or complementary substrates whereon the substrate potentials (VPWELL, VNWELL) are applied. The component (C) is put in waiting mode by decreasing the higher potential and increasing the lowre potential while the substrate potentials remain unchanged. The integrated circuit comprises the component (C), where the first potential of substrate (VDD0 or VSS0) is applied on a substrate of the first type component, and a potential limiter (R1) provides the component (C) as a substrate (VDD0 or VSS0), or the first limited potential (VDD1 or VSS1). The second potential of substrate (VSS0 or GND0) is applied to a substrate of the second type (p or n), and a potential limiter (R2) provides the supply potential (VSS or VDD), which is equal to the second potential of substrate (VSS0 or VDD0), or the second limited potential (VSS1 or VDD1). The potential limiter (R1) comprises a transistor (P0) whose source and substrate receive the first potential of substrate (VDD0), the gate receives a control signal (/REGUL) representative of the mode of functioning, and the first supply potential (VDD) is produced on the drain of the transistor; a transistor (N3) whose drain is connected to the source of the transistor (P0), and the source is connected to the gate by the intermediary of an inverter (11). The potential limiter (R2) comprises a transistor (N0) whose source and substrate receive the second potential of substrate (VSS0), the gate receives a control signal (REGUL), and the second supply potential (VSS) is produced on the drain of the transistor; and a transistor (P3) whose drain is connected to the source of the transistor (N0), and the source is connected to the gate by the intermediary of an inverter (I2).

    29.
    发明专利
    未知

    公开(公告)号：FR2824413B1

    公开(公告)日：2003-07-25

    申请号：FR0106091

    申请日：2001-05-07

    Applicant: ST MICROELECTRONICS SA

    Inventor： DRAY CYRILLE ,  FOURNEL RICHARD ,  THOMAS SIGRID

    IPC: G11C16/04 ,  G11C16/02

    Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the ouput signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

    Semiconductor device comprises strip fuse with extremity connected to integrated component and intermediate streamer thermal dissipation element
    30.
    发明专利
    Semiconductor device comprises strip fuse with extremity connected to integrated component and intermediate streamer thermal dissipation element 未知

    公开(公告)号：FR2826509A1

    公开(公告)日：2002-12-27

    申请号：FR0108427

    申请日：2001-06-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  CANDELIER PHILIPPE ,  COLOMBET NORBERT

    IPC: H01L23/367 ,  H01L23/525 ,  H01L23/552

    Abstract: The multilayer semiconductor device (1) of integrated electronic components comprises at least one electrical connection strip constituting a strip-fuse (2) in at least one layer, laid out so that it can be severed and whose extremity is connected to at least one integrated electronic component (4), and intermediate elements (5) for electrical connection and thermal dissipation. The intermediate elements (5) comprise at least one electrical connection strip extending in the form of a streamer (11), which is connected to the strip-fuse (2), through the thermal dissipation elements (6). The device also comprises a thermal screen (13) which is electrically insulated and placed in the immediate neighborhood of the strip-fuse (2), between the strip-fuse and the integrated electronic component. The intermediate elements (5) comprise the thermal dissipation strips (7) extending in different layers and connected by feedthroughs (8), in particular in a direction parallel to the strip-fuse. The screen (13) extends between the strip-fuse (2) and the intermediate elements (5), and the intermediate elements extensions (9) cross the screen (13). The screen (13) comprises strips spaced one from another and extended in different layers, placed one above another and connected by feedthroughs (15); this strip-screen extends perpendicular to the strip-fuse (2). The device comprises at least one protection diode (16) connected to the intermediate elements for electrical connection. The strip-fuse (2) can be severed by a laser beam directed to the bottom of a cavity (18).

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