公开(公告)号：DE602007004139D1

公开(公告)日：2010-02-25

申请号：DE602007004139

申请日：2007-03-16

Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA

Inventor： MONFRAY STEPHANE ,  SKOTNICKI THOMAS ,  DUTARTRE DIDIER ,  TALBOT ALEXANDRE

IPC: H01L29/786

Abstract: The method involves forming an intermediate semiconductor layer (6) above a substrate (2), where the layer contains an alloy of silicon and germanium. Source, drain and insulated gate regions (11,12,9) of a MOS transistor are formed above the semiconductor layer. The semiconductor layer is oxidized from a lower surface of the layer for increasing concentration of germanium in a channel of the transistor.

公开(公告)号：FR2860919B1

公开(公告)日：2009-09-11

申请号：FR0350665

申请日：2003-10-09

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： MONFRAY STEPHANE ,  HALIMAOUI AOMAR ,  CORONEL PHILIPPE ,  LENOBLE DAMIEN ,  FENOUILLET BERANGER CLAIRE

IPC: H01L21/762 ,  H01L21/336

Abstract: A region of monocrystalline silicon (20, 124 - 128) on insulator on silicon (24, 120) is destined to receive at least one component. The insulator (26) comprises some over-thickness (OT). Independent claims are also included for: (a) a component realised in such a region of monocrystalline silicon; (b) the fabrication of a semiconductor on insulator region; (c) the fabrication of a MOS transistor.

公开(公告)号：FR2899017A1

公开(公告)日：2007-09-28

申请号：FR0602467

申请日：2006-03-21

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

Inventor： MONFRAY STEPHANE ,  SKOTNICKI THOMAS ,  DUTARTRE DIDIER ,  TALBOT ALEXANDRE

IPC: H01L21/336 ,  H01L29/78

Abstract: L'invention concerne un procédé de fabrication d'un transistor MOS comprenant :a) la formation, au-dessus d'un substrat 2, d'une couche semiconductrice intermédiaire 6 contenant un alliage de silicium et de germanium,b) la réalisation des régions 11, 12, 9 de source, de drain et de grille isolée du transistor, au-dessus de la couche intermédiaire 6,c) l'oxydation de la couche intermédiaire 6 à partir de sa surface inférieure de façon à augmenter la concentration de germanium dans le canal du transistor.

公开(公告)号：FR2881416B1

公开(公告)日：2007-06-01

申请号：FR0550276

申请日：2005-01-31

Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： ABELE NICOLAS ,  ANCEY PASCAL ,  TALBOT ALEXANDRE ,  SEGUENI KARIM ,  BOUCHE GUILLAUME ,  SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  CASSET FABRICE

IPC: B81B3/00 ,  H03H3/007

Abstract: The microresonator has a resonant unit (160) made from monocrystalline silicon, and activation electrodes (120, 121) positioned close to the resonant unit. The unit (160) is placed in an opening in a semiconductor layer (110) that covers a substrate (100). The electrodes (120, 121) are formed in the layer and leveled with the opening. The unit (160) is in the shape of mushroom whose leg is fixed on the substrate. An independent claim is also included for a method of fabricating a microresonator.

公开(公告)号：FR2881416A1

公开(公告)日：2006-08-04

申请号：FR0550276

申请日：2005-01-31

Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： ABELE NICOLAS ,  ANCEY PASCAL ,  TALBOT ALEXANDRE ,  SEGUENI KARIM ,  BOUCHE GUILLAUME ,  SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  CASSET FABRICE

IPC: B81B3/00 ,  H03H3/007

Abstract: L'invention concerne un microrésonateur comprenant un élément résonant (160) en silicium monocristallin et au moins une électrode d'activation (120, 121) placée à proximité de l'élément résonant, dans lequel l'élément résonant est placé dans une ouverture d'une couche semiconductrice (110) recouvrant un substrat (100), l'électrode d'activation étant formée dans la couche semiconductrice et affleurant au niveau de l'ouverture.

公开(公告)号：FR2865850B1

公开(公告)日：2006-08-04

申请号：FR0401018

申请日：2004-02-03

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  CHANEMOUGAME DANIEL ,  MONFRAY STEPHANE

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786

公开(公告)号：FR2860919A1

公开(公告)日：2005-04-15

申请号：FR0350665

申请日：2003-10-09

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： MONFRAY STEPHANE ,  HALIMAOUI AOMAR ,  CORONEL PHILIPPE ,  LENOBLE DAMIEN ,  FENOUILLET BERANGER CLAIRE

IPC: H01L21/762 ,  H01L21/336

Abstract: A region of monocrystalline silicon (20, 124 - 128) on insulator on silicon (24, 120) is destined to receive at least one component. The insulator (26) comprises some over-thickness (OT). Independent claims are also included for: (a) a component realised in such a region of monocrystalline silicon; (b) the fabrication of a semiconductor on insulator region; (c) the fabrication of a MOS transistor.

公开(公告)号：FR2821483B1

公开(公告)日：2004-07-09

申请号：FR0102745

申请日：2001-02-28

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNIKI THOMAS ,  MONFRAY STEPHANE ,  VILLARET ALEXANDRE

IPC: H01L21/336 ,  H01L21/762

公开(公告)号：FR2839388A1

公开(公告)日：2003-11-07

申请号：FR0205539

申请日：2002-05-03

Applicant: ST MICROELECTRONICS SA

Inventor： MONFRAY STEPHANE ,  DUTARTRE DIDIER ,  BOEUF FREDERIC

IPC: H01S5/34 ,  H01L33/00 ,  H01L21/336 ,  H04L9/00

Abstract: An integrated circuit, incorporating a semiconductor device forming the source of a single photon, comprises on a silicon substrate (SB): (a) a MOS transistor (TR) having a grid in the shape of a mushroom, capable of delivering on its drain, in a controlled manner, a single electron in response to a control voltage applied on its grid; (b) at least one compatible silicon quantum box (BQ), electrically coupled to the drain region (D) of the transistor, and capable of emitting a single photon on the reception of a single electron emitted by the transistor. Independent claims are also included for: (a) a cryptographic device incorporating this integrated circuit; (b) a method for the fabrication of this integrated circuit; (c) a method for the emission of a single photon using this integrated circuit.

公开(公告)号：FR2818012B1

公开(公告)日：2003-02-21

申请号：FR0016174

申请日：2000-12-12

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  HAOND MICHEL

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/80 ,  H01L27/105

Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.