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    21.
    发明专利
    未知

    公开(公告)号：DE69520562D1

    公开(公告)日：2001-05-10

    申请号：DE69520562

    申请日：1995-05-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE ,  PISATI VALERIO

    IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78 ,  H03M1/00

    Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

    22.
    发明专利
    未知

    公开(公告)号：DE69426776D1

    公开(公告)日：2001-04-05

    申请号：DE69426776

    申请日：1994-12-27

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  DEMICHELI MARCO ,  PORTALURI SALVATORE

    IPC: G06G7/16 ,  G06G7/163

    Abstract: The error on the output signal produced by an analog multiplier comprising at least a differential output stage formed by a pair of emitter-coupled bipolar transistors (Q3, Q4), each driven by a predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function, attributable to the base currents of the bipolar transistors used, is compensated by generating replicas of the base current of the bipolar transistors (Q3, Q4) of said differential stage and forcing said replica currents on the output node of the respective predistortion stage (Q1, Q2). Various embodiments of different dissipative behaviours are described.

    23.
    发明专利
    未知

    公开(公告)号：DE69519663D1

    公开(公告)日：2001-01-25

    申请号：DE69519663

    申请日：1995-03-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  VAI GIANFRANCO ,  PORTALURI SALVATORE ,  DEMICHELI MARCO

    IPC: H03L7/093 ,  H03L7/089 ,  H03L7/099 ,  H03L7/107

    Abstract: A fully integrated, phase locked loop (PLL) having improved jitter characteristics exploits the same digital/analog converter (DAC) that is normally used for controlling the time constant of the low pass loop filter for controlling the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground that introduces a third pole in the loop's transfer function. In this way the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant, thus the dumping factor remains constant while the omega o of the PLL is varied.

    24.
    发明专利
    未知

    公开(公告)号：DE69515869T2

    公开(公告)日：2000-12-07

    申请号：DE69515869

    申请日：1995-09-14

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI DAVIDE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE

    IPC: H03G3/30 ,  G11B5/02 ,  H03G1/00 ,  H03G3/20

    Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

    25.
    发明专利
    未知

    公开(公告)号：DE69515869D1

    公开(公告)日：2000-04-27

    申请号：DE69515869

    申请日：1995-09-14

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI DAVIDE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE

    IPC: H03G3/30 ,  G11B5/02 ,  H03G1/00 ,  H03G3/20

    Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

    27.
    发明专利
    未知

    公开(公告)号：DE69833932D1

    公开(公告)日：2006-05-11

    申请号：DE69833932

    申请日：1998-04-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  OTTINI DANIELE ,  DEMICHELI MARCO ,  BOLLATI GIACOMINO

    IPC: G01R19/04 ,  H02M7/02 ,  G01R19/22 ,  H02M7/12 ,  H03F3/45

    Abstract: A full-wave rectifier for monitoring the amplitude of a differential analog signal (IN+, IN-) is composed of a differential Track&Hold stage (T&H) controlled by a first differential logic timing signal (TClk+, TClk-), tracking the differential analog input signal (IN+, IN-) during a tracking phase that corresponds to a high logic stage of the first differential timing signal (TClk+, TClk-), producing a differential output signal that is a replica of the input signal and storing it during a successive storing phase that corresponds to a low logic state of the first differential timing signal (TClk+, TClk-); a first differential output amplifier ( @ ) having inputs coupled to the output of the Track&Hold stage (T&H); a differential bistable circuit (LATCH-ECL), controlled by a second differential logic timing signal (DClk+, DClk-), having inputs coupled to the differential outputs of the first amplifier ( @ ) and producing a third differential logic control signal (S+, S-); a second multiplexed amplifier (Analog-Amp @ ), controlled by the third differential control signal (S+, S-), having inputs coupled to the output of the Track&Hold stage (T&H) and outputting a differential analog signal (OUT+, OUT-) of amplitude function of the amplitude of the differential input signal (IN+, IN-); a timing circuit (T @ C @ ) receiving at an input a differential logic synchronism signal (Clk+, Clk-) and generating the first differential timing signal (TClk+, TClk-) of said Track&Hold stage (T&H) and the second differential timing signal (DClk+, DClk-) of said bistable circuit (LATCH-ECL).

    29.
    发明专利
    未知

    公开(公告)号：DE69812369D1

    公开(公告)日：2003-04-24

    申请号：DE69812369

    申请日：1998-12-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  OTTINI DANIELE ,  SAVO ALESSANDRO

    IPC: G11B20/10 ,  G11B20/00 ,  H03M1/10 ,  H03M1/12 ,  H04L27/08

    Abstract: A read and analog-to-digital data conversion channel comprising preamplifying circuits (Pre-Amp), automatic gain control circuits (VGA), harmonics filters (MRA), equalizing low pass filters (LPF), a time interleaved analog-to-digital converter (INTERLEAVED ATOD) including a pair of identical analog/digital converters (ATOD_EVEN, ATOD_ODD) functioning in parallel and at a half clock frequency, subdividing the signal path into two parallel paths through said two identical converters, one for even bits and the other for odd bits, and a digital post-processing block (DIGITAL Post Processing) fed by two output streams of said time interleaved converter (INTERLEAVED ATOD) and outputting a reconstructed data stream (DATA) and controlling said circuits, through dedicated digital-to-analog converters (DAC_VGA, DAC_MRA, DAC_FC, DAC_BOOST), means for compensating the offset of the digital-to-analog converters contained in said pair of identical analog-to-digital converters (ATOD_EVEN, ATOD_ODD) of said time interleaved converter (INTERLEAVED ATOD), controlled by said post-processing block (DIGITAL Post Processing) through a digital-to-analog converter, further comprises two distinct offset compensating circuits, each composed of an offset compensating stage (OFFSET_EVEN_STAGE, OFFSET_ODD_STAGE) independently controlled by said digital post-processing block through a dedicated digital-to-analog converter (DAC_OFF_E, DAC_OFF_O), preventing appearance of spurious patterns in frequency domain.

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