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公开(公告)号：DE60041037D1
公开(公告)日：2009-01-22
申请号：DE60041037
申请日：2000-03-21
Applicant: ST MICROELECTRONICS SRL
Inventor： ROLANDI PAOLO
Abstract: A nonvolatile memory (1) having a NOR architecture has a memory array (2) including a plurality of memory cells (3) arranged in rows and columns in NOR configuration, the memory cells (3) arranged on a same column being connected to one of a plurality of bit lines (11); and a column decoder (6). The column decoder comprises a plurality of selection stages (17), each of which is connected to respective bit lines (11) and receives first bit line addressing signals (YM0, ..., YM7). The selection stages (17) comprise word programming selectors (28) controlled by the first bit line addressing signals (YM0, ..., YM7) and supplying a programming voltage (70) to only one of the bit lines (11) of each selection stage (17). Each selection stage (17) moreover comprises a string programming selection circuit (29, 30) controlled by second bit line addressing signals (S0, ..., S7) thereby simultaneously supplying the programming voltage (70) to a plurality of the bit lines (11) of each selection stage (17).
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公开(公告)号：DE60033818T2
公开(公告)日：2007-11-15
申请号：DE60033818
申请日：2000-09-18
Applicant: ST MICROELECTRONICS SRL
Inventor： ROLANDI PAOLO , MONTANARO MASSIMO , ODDONE GIORGIO
Abstract: A method for programming a multilevel non-volatile memory with a reduced number of pins, wherein at least one address pin (A1, A2) of the memory is used as a write synchronization signal.
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公开(公告)号：DE60033818D1
公开(公告)日：2007-04-19
申请号：DE60033818
申请日：2000-09-18
Applicant: ST MICROELECTRONICS SRL
Inventor： ROLANDI PAOLO , MONTANARO MASSIMO , ODDONE GIORGIO
Abstract: A method for programming a multilevel non-volatile memory with a reduced number of pins, wherein at least one address pin (A1, A2) of the memory is used as a write synchronization signal.
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公开(公告)号：DE69831155D1
公开(公告)日：2005-09-15
申请号：DE69831155
申请日：1998-10-29
Applicant: ST MICROELECTRONICS SRL
Inventor： RIVA MARCO , ROLANDI PAOLO , MONTANARO MASSIMO
Abstract: A method for testing virgin memory cells in a multilevel memory device which comprises a plurality of memory cells, the particularity of which consists of the fact that it comprises the steps of: reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not; determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell; the at least one reference memory cell being chosen with a gradually higher threshold; when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.
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公开(公告)号：DE69633774D1
公开(公告)日：2004-12-09
申请号：DE69633774
申请日：1996-03-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , ROLANDI PAOLO , FONTANA MARCO , BARCELLA ANTONIO
Abstract: A reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders, characterized in that the memory is divided into at least two memory half-matrices that are arranged on different half-planes, and in that the circuit comprises, for each one of the at least two memory half-matrices, a reference unit (3i) for each one of the at least two memory half-matrices and an associated unit (4) for reproducing the propagation of the signals along the reference unit, the reference unit (3i) and the associated propagation reproduction unit (4) having a structure that is identical to each generic word line of the memory device, the reference and propagation reproduction units of one of the at least two memory half-matrices being activatable upon selection of a memory cell in the other one of the at least two memory half-matrices, in order to provide a reference that is synchronous and symmetrical with respect to the selection of the memory cell for reading it and so as to preset, according to the propagation reproduction unit (4), the conditions for starting correct and certain reading of the selected memory cell.
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Patent Agency Ranking
公开(公告)号：DE69726136D1
公开(公告)日：2003-12-18
申请号：DE69726136
申请日：1997-08-29
Applicant: ST MICROELECTRONICS SRL
Inventor： ROLANDI PAOLO , GASTALDI ROBERTO , CALLIGARO CRISTIANO
Abstract: The present invention relates to a circuit for generating a regulated voltage (RV), in particular for gate terminals of non-volatile memory cells of the floating gate type, which comprises a generator circuit (OSC,CHP) adapted to generate an unregulated voltage (VCHP) on its output, a comparator circuit coupled to the output of the generator circuit (OSC,CHP), including a reference element consisting of a non-volatile memory cell (REFC) of the floating gate type and adapted to output an electric error signal (ID) tied to the difference between the unregulated voltage (VCHP) and the threshold voltage of the cell (REFC), and a regulator circuit (CSEL,CBIAS,IVC,DRV,TR) coupled to the output of the comparator circuit and operative to regulate the unregulated voltage (VCHP) based on the value of the electric error signal (ID). Through the present circuit, the regulated voltage (RV) is made programmable and tied to the parameters of the memory cell (REFC).
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公开(公告)号：DE69627318D1
公开(公告)日：2003-05-15
申请号：DE69627318
申请日：1996-08-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ROLANDI PAOLO , CALLIGARIO CRISTIANO , MANSTRETTA ALESSANDRO , TORELLI GUIDO
Abstract: In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input (RADR,CADR), each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.
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公开(公告)号：DE69427461D1
公开(公告)日：2001-07-19
申请号：DE69427461
申请日：1994-03-31
Applicant: ST MICROELECTRONICS SRL
Inventor： ROLANDI PAOLO
Abstract: A non-volatile memory element with dual programmable cells and associated read circuit, which comprises a circuit (LATCH) of the bistable type connected between the two memory cells, to which it is coupled through first and second switching circuit elements (SW1, SW2). Such switching elements enable a single initial write step by one of the two memory cells only, and thereafter, enable connection of the clear cell and the programmed cell to the bistable circuit.
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公开(公告)号：DE69128494D1
公开(公告)日：1998-02-05
申请号：DE69128494
申请日：1991-04-04
Applicant: ST MICROELECTRONICS SRL
Inventor： ROLANDI PAOLO , MACCALLI MARCO , DALLABORA MARCO
IPC: H03K19/0185 , H03K19/003 , H03K19/0175
Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.
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公开(公告)号：DE60039587D1
公开(公告)日：2008-09-04
申请号：DE60039587
申请日：2000-05-31
Applicant: ST MICROELECTRONICS SRL
Inventor： ROLANDI PAOLO , MONTANARO MASSIMO , ODDONE GIORGIO
Abstract: The invention relates to a circuit structure (1) for programming data in reference cells (3) of an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix of multi-level memory cells and at least one corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell (3) is incorporated, along with other cells of the same type, to a reference cell sub-matrix (4) which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode. The bit lines of the sub-matrix (4) branch off to a series of switches (9) which are individually operated by respective control signals REF(i) issued from a logic circuit (8) with the purpose of selectively connecting the bit lines to a single external I/O terminal (10) through a single addressing line (11) of the access DMA mode.
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