中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

60 records (took 0.032 seconds)

    Staircase adaptive voltage generator circuit
    21.
    发明公开
    Staircase adaptive voltage generator circuit 失效
    Adaptiver Treppenspannungserzeugerstromkreis

    公开(公告)号：EP0862270A1

    公开(公告)日：1998-09-02

    申请号：EP97830084.6

    申请日：1997-02-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele, Vincenzo ,  Manstretta, Alessandro ,  Rolandi, Paolo ,  Torelli, Guido

    IPC: H03K4/02 ,  G05F1/46

    CPC classification number: G05F1/465 ,  H03K4/023

    Abstract: A stair-case adaptive voltage generator circuit, which circuit comprises a first capacitor (CB) connected between a first voltage reference (Vref) and an output operational amplifier (CA), through first (T1 and second (T4) switches, respectively.
    The terminals of the capacitor are also connected to a second voltage reference (Vinit) through third (T3) and fourth (T2) switches, respectively.
    A second capacitor (CA), in series with a fifth switch (CNT), is connected in parallel to the first capacitor (CB).

    Abstract translation: 一个阶梯式自适应电压发生器电路，该电路包括分别通过第一（T1和第二（T4）开关连接在第一电压基准（Vref）和输出运算放大器（CA）之间的第一电容器（CB）。 电容器的端子也分别通过第三（T3）和第四（T2）开关连接到第二参考电压（Vinit），与第五开关（CNT）串联的第二电容器（CA）并联 到第一个电容（CB）

    Non-volatile memory electronic device with NAND structure being monolithically integrated on semiconductor
    25.
    发明公开
    Non-volatile memory electronic device with NAND structure being monolithically integrated on semiconductor 有权
    Integriete Schaltung mitNichtflüchtigemSpeicher des NAND-Typs

    公开(公告)号：EP1713084A1

    公开(公告)日：2006-10-18

    申请号：EP05425209.3

    申请日：2005-04-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi ,  Rolandi, Paolo

    IPC: G11C16/16

    CPC classification number: G11C16/0483 ,  G11C16/12

    Abstract: The invention relates to a non volatile memory electronic device (20) integrated on semiconductor with an architecture comprising at least one memory matrix (21) organised in rows or word lines (WL) and columns or bit lines (BL) of memory cells. The matrix is divided into at least a first (23) and a second memory portions (23a) having different access speed, said first (23) and second memory portions (23a) sharing the structures of the bit lines (BL) which correspond to one another and one by one and are electrically interrupted by controlled switches (29) placed between the first (23) and the second portion (23a).

    Abstract translation: 本发明涉及一种集成在半导体上的非易失性存储器电子器件（20），该非易失性存储器电子器件（20）具有包括以行或字线（WL）和存储器单元的列或位线（BL）组织的至少一个存储器矩阵（21）的架构。 矩阵被分成至少具有不同访问速度的第一存储器部分（23）和第二存储器部分（23a），所述第一存储器部分（23）和第二存储器部分（23a）共享位线（BL）的结构， 彼此并且一个接一个地被置于第一（23）和第二部分（23a）之间的受控开关（29）电中断。

    Method and circuit for testing virgin memory cells in a multilevel memory device
    27.
    发明授权
    Method and circuit for testing virgin memory cells in a multilevel memory device 有权
    用于非编程的存储器单元的在多电平存储器测试的方法和装置

    公开(公告)号：EP0997913B1

    公开(公告)日：2005-08-10

    申请号：EP98830654.4

    申请日：1998-10-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Riva, Marco ,  Rolandi, Paolo ,  Montanaro, Massimo

    IPC: G11C29/00 ,  G11C11/56 ,  G06F11/20

    CPC classification number: G11C29/50 ,  G06F2201/81 ,  G11C11/56 ,  G11C11/5642 ,  G11C2029/5006 ,  G11C2211/5634

    Abstract: A method for testing virgin memory cells in a multilevel memory device which comprises a plurality of memory cells, the particularity of which consists of the fact that it comprises the steps of: reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not; determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell; the at least one reference memory cell being chosen with a gradually higher threshold; when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.

    Method and circuit for generating a gate voltage in non-volatile memory devices
    30.
    发明公开
    Method and circuit for generating a gate voltage in non-volatile memory devices 失效
    方法和电路，用于产生用于非易失性存储器阵列的栅极电压

    公开(公告)号：EP0899742A1

    公开(公告)日：1999-03-03

    申请号：EP97830435.0

    申请日：1997-08-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo ,  Gastaldi, Roberto ,  Calligaro, Cristiano

    IPC: G11C11/00 ,  G11C16/06 ,  G11C11/56

    CPC classification number: G11C11/5642 ,  G11C8/14 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/30 ,  G11C29/00 ,  G11C2211/5634

    Abstract: The present invention relates to a circuit for generating a regulated voltage (RV), in particular for gate terminals of non-volatile memory cells of the floating gate type, which comprises a generator circuit (OSC,CHP) adapted to generate an unregulated voltage (VCHP) on its output, a comparator circuit coupled to the output of the generator circuit (OSC,CHP), including a reference element consisting of a non-volatile memory cell (REFC) of the floating gate type and adapted to output an electric error signal (ID) tied to the difference between the unregulated voltage (VCHP) and the threshold voltage of the cell (REFC), and a regulator circuit (CSEL,CBIAS,IVC,DRV,TR) coupled to the output of the comparator circuit and operative to regulate the unregulated voltage (VCHP) based on the value of the electric error signal (ID). Through the present circuit, the regulated voltage (RV) is made programmable and tied to the parameters of the memory cell (REFC).

    Abstract translation: 本发明涉及一种电路，用于产生调节电压（RV），特别是用于浮置栅极型，其包括生成器电路（OSC，CHP）angepasst产生的非易失性存储单元的栅极端子（在未调节的电压 VCHP）在其输出端，耦合到所述发生器电路（OSC，CHP）包括参考元件由...组成的浮栅型的非易失性存储单元（REFC）的和angepasst电动错误的输出的输出端的比较器电路 绑在未调节的电压（VCHP）和细胞（REFC）的阈值电压，和调节器电路之间的差信号（ID）（CSEL，CBIAS，IVC，DRV，TR）耦合到所述比较器电路的输出端和 可操作以调节基于电动误差信号（ID）的值的未稳压电压（VCHP）。 通过本电路中，经调节的电压（RV）是由可编程的，并且依赖于存储单元（REFC）的参数。

Patent Agency Ranking