Abstract:
A process for manufacturing an array of cells in a body (1) of semiconductor material wherein a common conduction region (11) of a first conductivity type and a plurality of shared control regions (12), of a second conductivity type, are formed in the body. The shared control regions (12) extend on the common conduction region (11) and are laterally delimited by insulating regions (32). Then, a grid-like layer (36) is formed on the body (1) to delimit a first plurality of empty regions (38) directly overlying the body and conductive regions of semiconductor material and the first conductivity type (44) are formed by filling the first plurality of empty regions (38), each conductive region forming, together with the common conduction region and an own shared control region (12), a bipolar junction transistor (20).
Abstract:
Process for the manufacture of a non volatile memory with memory cells arranged in lines (2) and columns (3) in a matrix structure, with source lines (10) extending parallelly and intercalate to said lines (1), said source lines (10) formed by active regions intercalated to field oxide zones (4), said process comprising steps for the definition of active areas of said columns (3) of said matrix of non volatile memory cells and the definition of said field oxide zones (4), subsequent steps for the definition of the lines (2) of said matrix of non volatile memory cells, a following step for the definition of said source lines (10). In said step for the definition of the source lines a process step comprising a selective introduction of dopant is foreseen so to form a layer of buried silicon with high concentration of dopant (30), said layer of buried silicon (30) being formed to such a depth to coincide with the regions of silicon the underlying field oxide zones (4), a following introduction of dopant in said active regions of the source lines (10) to superficially contact said layer of buried silicon (30).
Abstract:
A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4) . A reference cell (2a) formed by an own phase change memory element (3a) and an own selection switch (4a) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
Abstract:
A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells (33), arranged in rows and columns; and forming a plurality of resistive bit lines (35) for connecting PCM cells (33) arranged on a same column, each resistive bit lines (35) comprising a respective phase change material portion (31'), covered by a respective barrier portion (32'). After forming the resistive bit lines (35), electrical connection structures (45, 52) for the resistive bit lines (35) are formed directly in contact with the barrier portions (32') of the resistive bit lines (35).
Abstract:
A process for manufacturing phase change memory cells includes the step of forming a heater element (25a) in a semiconductor wafer (10) and a storage region (31a) of a phase change material on and in contact with the heater element (25a). In order to form the heater element (25a) and the phase change storage region (31a) a heater structure is first formed and a phase change layer (31) is deposited on and in contact with the heater structure. Then, the phase change layer (31) and the heater structure are defined by subsequent self-aligned etch steps.
Abstract:
The present invention proposes a Field Programmable Gate Array (FPGA) device (100) comprising a plurality of configurable electrical connections (115 1 -115 2 ,115 1 -115 3 ), a plurality of controlled switches (205), each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit (125) including an arrangement of a plurality of control cells (200). Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element (210,215) adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element (P1;F1) coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.