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    Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions
    22.
    发明公开
    Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions 审中-公开
    对于具有选择晶体管的双极单元阵列具有突出的导电区域的制造方法

    公开(公告)号：EP2015357A1

    公开(公告)日：2009-01-14

    申请号：EP07425423.6

    申请日：2007-07-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Benvenuti, Augusto ,  Cappelletti, Paolo ,  Bez, Roberto ,  Pirovano, Agostino

    IPC: H01L21/8229 ,  H01L27/102 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

    Abstract: A process for manufacturing an array of cells in a body (1) of semiconductor material wherein a common conduction region (11) of a first conductivity type and a plurality of shared control regions (12), of a second conductivity type, are formed in the body. The shared control regions (12) extend on the common conduction region (11) and are laterally delimited by insulating regions (32). Then, a grid-like layer (36) is formed on the body (1) to delimit a first plurality of empty regions (38) directly overlying the body and conductive regions of semiconductor material and the first conductivity type (44) are formed by filling the first plurality of empty regions (38), each conductive region forming, together with the common conduction region and an own shared control region (12), a bipolar junction transistor (20).

    Abstract translation: 于一体的制造单元的阵列的方法（1）的半导体材料的worin的第一导电类型的公共导电区（11）和一个第二导电类型的共享控制区域（12）的复数，在形成 身体。 共享控制区（12）上的公共导电区（11）延伸，并且尾盘反弹通过绝缘区域（32）分隔。 然后，网格状层（36）形成在所述主体（1）来分隔空区域的第一多个（38）直接覆盖所述主体和半导体材料的导电区域和第一导电类型（44）由形成 填充空区域（38），每个导电区域上形成的第一多个，与普通传导区在一起并且连接到自己的共享控制区域（12），双极结型晶体管（20）。

    Process of manufacture of a non volatile memory with electric continuity of the common source lines
    24.
    发明公开
    Process of manufacture of a non volatile memory with electric continuity of the common source lines 审中-公开
    来自莱顿根的Herstellungsverfahren von Festwertspeichern mit elektrischerKontinuitätgemeinsamer

    公开(公告)号：EP1045440A1

    公开(公告)日：2000-10-18

    申请号：EP99830211.1

    申请日：1999-04-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bez, Roberto ,  Riva, Caterina ,  Servalli, Giorgio

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521

    Abstract: Process for the manufacture of a non volatile memory with memory cells arranged in lines (2) and columns (3) in a matrix structure, with source lines (10) extending parallelly and intercalate to said lines (1), said source lines (10) formed by active regions intercalated to field oxide zones (4), said process comprising steps for the definition of active areas of said columns (3) of said matrix of non volatile memory cells and the definition of said field oxide zones (4), subsequent steps for the definition of the lines (2) of said matrix of non volatile memory cells, a following step for the definition of said source lines (10). In said step for the definition of the source lines a process step comprising a selective introduction of dopant is foreseen so to form a layer of buried silicon with high concentration of dopant (30), said layer of buried silicon (30) being formed to such a depth to coincide with the regions of silicon the underlying field oxide zones (4), a following introduction of dopant in said active regions of the source lines (10) to superficially contact said layer of buried silicon (30).

    Abstract translation: 用于制造具有以矩阵结构的线（2）和列（3）排列的存储单元的非易失性存储器的方法，源极线（10）平行并插入所述线（1），所述源极线（10） ）由所述有源区插入到场氧化物区（4）中形成，所述方法包括用于定义所述非易失性存储单元矩阵的所述列（3）的有效面积和所述场氧化物区（4）的定义的步骤， 用于定义非易失性存储器单元的所述矩阵的行（2）的后续步骤，用于定义所述源极线（10）的后续步骤。 在用于定义源极线的所述步骤中，预期包括选择性引入掺杂剂的工艺步骤，以便形成具有高浓度掺杂剂（30）的掩埋硅层，所述掩埋硅层（30）形成为 深度与硅的区域与下面的场氧化物区域（4）重合，随后在源极线（10）的所述有源区域中引入掺杂剂以表面接触所述掩埋硅层（30）。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby
    27.
    发明公开
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby 有权
    一种用于制备在铜镶嵌技术相变存储器阵列以及将相变存储器相应产生阵列处理

    公开(公告)号：EP1505656A1

    公开(公告)日：2005-02-09

    申请号：EP03425536.4

    申请日：2003-08-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto

    IPC: H01L27/24

    CPC classification number: H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells (33), arranged in rows and columns; and forming a plurality of resistive bit lines (35) for connecting PCM cells (33) arranged on a same column, each resistive bit lines (35) comprising a respective phase change material portion (31'), covered by a respective barrier portion (32'). After forming the resistive bit lines (35), electrical connection structures (45, 52) for the resistive bit lines (35) are formed directly in contact with the barrier portions (32') of the resistive bit lines (35).

    Abstract translation: 一种用于制造相变存储器阵列的方法，包括以下步骤：形成PCM单元的多个（33），以行和列布置; 以及形成电阻的位线用于连接PCM单元布置在同一列有多个（35）（33），每个电阻的位线（35），其包括respectivement相变材料部分（31“）中，由一个respectivement阻挡部分覆盖（ 32“）。 形成用于电阻的位线电阻的位线（35），电连接结构（45，52）之后，（35）直接与所述电阻的位线（35）的阻挡部分（32“）接触而形成。

    Self-aligned process for manufacturing phase change memory cells
    28.
    发明公开
    Self-aligned process for manufacturing phase change memory cells 有权
    Selbstjustiertes Verfahren zur Herstellung von Phasenwechselspeicherzellen

    公开(公告)号：EP1729355A1

    公开(公告)日：2006-12-06

    申请号：EP05104879.1

    申请日：2005-06-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Varesi, Enrico ,  Pirovano, Agostino ,  Petruzza, Pietro

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element (25a) in a semiconductor wafer (10) and a storage region (31a) of a phase change material on and in contact with the heater element (25a). In order to form the heater element (25a) and the phase change storage region (31a) a heater structure is first formed and a phase change layer (31) is deposited on and in contact with the heater structure. Then, the phase change layer (31) and the heater structure are defined by subsequent self-aligned etch steps.

    Abstract translation: 用于制造相变存储单元的方法包括在半导体晶片（10）中形成加热元件（25a）和在与加热器元件（25a）接触并与之接触的相变材料的存储区域（31a）的步骤。 为了形成加热器元件（25a）和相变储存区域（31a），首先形成加热器结构，并且相变层（31）沉积在加热器结构上并与加热器结构接触。 然后，通过随后的自对准蚀刻步骤限定相变层（31）和加热器结构。

    An improved field programmable gate array device
    30.
    发明公开
    An improved field programmable gate array device 有权
    Ein verbicultes feldprogrammierbares门阵列

    公开(公告)号：EP1519489A1

    公开(公告)日：2005-03-30

    申请号：EP03021455.5

    申请日：2003-09-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  De Sandre, Guido ,  Bez, Roberto

    IPC: H03K19/177

    CPC classification number: G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

    Abstract: The present invention proposes a Field Programmable Gate Array (FPGA) device (100) comprising a plurality of configurable electrical connections (115 1 -115 2 ,115 1 -115 3 ), a plurality of controlled switches (205), each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit (125) including an arrangement of a plurality of control cells (200). Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element (210,215) adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element (P1;F1) coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

    Abstract translation: 本发明提出了一种包括多个可配置电连接（1151-1152,1151-1153）的现场可编程门阵列（FPGA）装置，多个受控开关（205），每个控制开关适于启动/ 响应于开关控制信号激活至少一个相应的电连接，以及包括多个控制单元（200）的布置的控制单元（125）。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件（210,215），其适于以易失性方式存储对应于至少一个 控制开关，并且向控制开关提供与存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件（P1; F1），非易失性存储元件适于以非易失性方式存储控制逻辑值。

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