中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.028 seconds)

    An improved page buffer for a programmable memory device
    23.
    发明公开
    An improved page buffer for a programmable memory device 有权
    一种改进的可编程存储器设备的页面缓冲区

    公开(公告)号：EP1598831A1

    公开(公告)日：2005-11-23

    申请号：EP04102232.8

    申请日：2004-05-20

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Khouri, Osama ,  Zanardi, Stefano ,  Martinozzi, Giulio

    IPC: G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/26

    Abstract: A page buffer ( 130 ) for an electrically programmable memory including a plurality of memory cells ( 110 ) forming a plurality of memory pages, the page buffer comprising at least one register ( 130m,130c ) for at least temporarily storing data read from or to be written into the memory cells of a selected memory page of said plurality, the at least one register comprising a plurality of latches ( 230m ), each latch being operatively associated with at least one respective signal line ( BLe,BLo,I/O-LINE ) transporting the data bit temporarily stored in the latch. A buffer element ( BUF ) is provided for decoupling an output of the latch from the respective signal line, the latch using the respective buffer element for driving the signal line according to the data bit stored therein.

    Abstract translation: 一种用于电可编程存储器的页缓冲器（130），所述电可编程存储器包括形成多个存储器页的多个存储器单元（110），所述页缓冲器包括至少一个寄存器（130m，130c），用于至少暂时存储从或者到 被写入所述多个选定存储页中的存储单元，所述至少一个寄存器包括多个锁存器（230m），每个锁存器与至少一个相应信号线（BLe，BLo，I / O- LINE）传输临时存储在锁存器中的数据位。 提供缓冲器元件（BUF），用于将锁存器的输出与相应的信号线去耦，锁存器使用相应的缓冲器元件根据存储在其中的数据位来驱动信号线。

    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device
    25.
    发明公开
    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device 有权
    在非易失性更通常高密度存储器和相关联的换能器为模拟/数字转换的方法

    公开(公告)号：EP1211812A3

    公开(公告)日：2003-02-12

    申请号：EP00127649.2

    申请日：2000-11-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

    IPC: H03M1/14 ,  G11C11/56

    CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

    Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg). The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB). The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.

    Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude
    28.
    发明公开
    Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude 有权
    一种用于使用阶梯状的电压脉冲与步骤之间的可变距离编程非易失性存储器单元以编程和测试算法方法

    公开(公告)号：EP1249842A1

    公开(公告)日：2002-10-16

    申请号：EP01830247.1

    申请日：2001-04-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Gregori, Stefano ,  Micheloni, Rino ,  Pierin, Andrea ,  Khouri, Osama ,  Torelli, Guido

    IPC: G11C16/12

    CPC classification number: G11C11/5628 ,  G11C16/12

    Abstract: Described herein is a method for programming a nonvolatile memory cell (1), which envisages applying in succession, to the gate terminal (2) of the memory cell (1), at least a first and a second programming pulse trains (F1, F2) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Advantageously, the programming method envisages applying, to the gate terminal (2) of the memory cell (1) and before the first programming pulse train (F1), also a third programming pulse train (F0; F3) with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train (F1) and substantially equal to the amplitude increment in the second programming pulse train (F2), or else may be greater than the amplitude increment in the first programming pulse train (F1).

    Abstract translation: 该方法涉及将相继地向存储单元的控制端子，至少两个编程脉冲串（F1，F2）与脉冲幅度在楼梯方式增加。 一个脉冲，并在第一编程脉冲串（F1）的下一个之间的幅度增量比一个脉冲，并在第二编程脉冲串（F2）的下一个之间的幅度增量越大。 从所述第一编程脉冲来训练到第二转换时当存储器单元具有与一个参考值的预先设定的关系的阈值电压。

Patent Agency Ranking