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公开(公告)号：US11895773B2
公开(公告)日：2024-02-06
申请号：US17853933
申请日：2022-06-30
Applicant: Unimicron Technology Corp.
Inventor： Shih-Lian Cheng
CPC classification number: H05K1/116 , H05K1/0222 , H05K2201/0195 , H05K2201/09509
Abstract: A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole, a first annular retaining wall, and a second annular retaining wall. The conductive through hole penetrates through the third dielectric layer, a second dielectric layer, and the fourth dielectric layer. The conductive through hole is electrically connected to the first external circuit layer and the second external circuit layer. The first annular retaining wall is disposed in the third dielectric layer, surrounds the conductive through hole, and is electrically connected to the first external circuit layer and the first inner circuit layer. The second annular retaining wall is disposed in the fourth dielectric layer, surrounds the conductive through hole, and connects to the second external circuit layer and the second inner circuit layer electrically.
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公开(公告)号：US11859302B2
公开(公告)日：2024-01-02
申请号：US17705405
申请日：2022-03-28
Applicant: Unimicron Technology Corp.
Inventor： Heng-Ming Nien , Chih-Chiang Lu , Chih-Kai Chan , Shih-Lian Cheng
Abstract: An electroplating apparatus includes an anode and a cathode, a power supply, a regulating plate, and a controller. The power supply is electrically connected to the anode and the cathode. The regulating plate is disposed between the anode and the cathode. The regulating plate includes an insulation grid plate and a plurality of wires. The controller is electrically connected to the plurality of wires to control a state of an electromagnetic field around the plurality of wires. An electroplating method is also provided.
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公开(公告)号：US11737206B2
公开(公告)日：2023-08-22
申请号：US17873153
申请日：2022-07-26
Applicant: Unimicron Technology Corp.
Inventor： Shih-Lian Cheng
IPC: H05K1/02
CPC classification number: H05K1/0222 , H05K1/024 , H05K2201/096 , H05K2201/0959 , H05K2201/09509 , H05K2201/09536
Abstract: A circuit board structure includes a first dielectric layer, first and second inner circuit layers, a conductive connection layer, a second dielectric layer, two third dielectric layers, third and fourth inner circuit layers, two conductive through vias, first and second annular retaining walls, two fourth dielectric layers, first and second external circuit layers, and third and fourth annular retaining walls. The conductive through vias penetrate the third and second dielectric layers and electrically connect the third and fourth inner circuit layers. The first and second annular retaining walls surround the conductive through vias and electrically connect the third and first and the fourth and second inner circuit layers. The third and fourth annular retaining walls are respectively disposed in the fourth dielectric layers and electrically connect the first external circuit layer and the third inner circuit layer and the second external circuit layer and the fourth inner circuit layer.
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公开(公告)号：US20230240014A1
公开(公告)日：2023-07-27
申请号：US17685404
申请日：2022-03-03
Applicant: Unimicron Technology Corp.
Inventor： Ming-Hao Wu , Shih-Lian Cheng
CPC classification number: H05K3/0094 , H05K3/429 , H05K1/144 , H05K1/111
Abstract: A printed circuit board stack structure includes a first printed circuit board, a second printed circuit board, and a filling glue layer. The first printed circuit board has at least one overflow groove, and includes first pads and a retaining wall surrounding the first pads. The second printed circuit board is disposed on the first printed circuit board, and includes second pads and conductive pillars located on some of the second pads. The conductive pillars are respectively connected to some of the first pads to electrically connect the second printed circuit board to the first printed circuit board. The filling glue layer fills between the first and the second printed circuit boards, and covers the first pads, the second pads, and the conductive pillars. The retaining wall blocks the filling glue layer so that a portion of the filling glue layer is accommodated in the overflow groove.
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公开(公告)号：US20230120741A1
公开(公告)日：2023-04-20
申请号：US17700531
申请日：2022-03-22
Applicant: Unimicron Technology Corp.
Inventor： Heng-Ming Nien , Cho-Ying Wu , Shih-Lian Cheng
Abstract: Provided is an electroplating apparatus including an electroplating tank, an anode and a cathode, a power supply, and a regulating plate. The electroplating tank accommodates electrolyte. Both the anode and the cathode are disposed in the electroplating tank. The power supply is electrically connected to the anode and the cathode. The regulating plate is disposed between the anode and the cathode. The regulating plate includes a plurality of mesh openings and a plurality of metal sheets, and at least part of the metal sheets is electrically connected with the cathode. An electroplating method is also provided.
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Patent Agency Ranking
公开(公告)号：US20220230949A1
公开(公告)日：2022-07-21
申请号：US17498757
申请日：2021-10-12
Applicant: Unimicron Technology Corp.
Inventor： Chih-Chiang Lu , Hsin-Ning Liu , Jun-Rui Huang , Pei-Wei Wang , Ching Sheng Chen , Shih-Lian Cheng
Abstract: A circuit board includes a first external circuit layer, a first substrate, a second substrate, a third substrate, and a conductive through hole structure. The first substrate includes conductive pillars electrically connecting the first external circuit layer and the second substrate. The second substrate has an opening and includes a first dielectric layer. The opening penetrates the second substrate, and the first dielectric layer fills the opening. The third substrate includes an insulating layer, a second external circuit layer, and conductive holes. A conductive material layer of the conductive through hole structure covers an inner wall of a through hole and electrically connects the first and the second external circuit layers to define a signal path. The first external circuit layer, the conductive pillars, the second substrate, the conductive holes and the second external circuit layer are electrically connected to define a ground path surrounding the signal path.
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公开(公告)号：US20170273191A1
公开(公告)日：2017-09-21
申请号：US15273727
申请日：2016-09-23
Applicant: Unimicron Technology Corp.
Inventor： Shih-Lian Cheng
Abstract: A manufacturing method of a circuit board and a stamp are provided. The method includes the following steps. A circuit pattern and a dielectric layer covering the circuit pattern are formed on a dielectric substrate. A conductive via connected to the circuit pattern is formed in the dielectric layer. A photoresist material layer is formed on the dielectric layer. An imprinting process is performed on the photoresist material layer using a stamp to form a patterned photoresist layer, wherein the pressing side of the stamp facing the circuit pattern becomes sticky when subjected to pressure so as to catch photoresist residue from the photoresist material layer in the imprinting process. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed.
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公开(公告)号：US20140174804A1
公开(公告)日：2014-06-26
申请号：US13726230
申请日：2012-12-24
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen , Shih-Lian Cheng
CPC classification number: H05K3/007 , H01L23/5389 , H01L24/19 , H01L2924/12042 , H05K1/18 , H05K1/183 , H05K1/185 , H05K3/0011 , H05K3/06 , H05K3/30 , H05K3/423 , H05K3/465 , H05K2203/0723 , H05K2203/1469 , Y10T29/4913 , H01L2924/00
Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. Moreover, the electrical device package structure is also provided.
Abstract translation: 提供了包括以下步骤的电气设备的包装方法。 提供了包括基板和第一导电图案的电路板。 具有电极的电气装置设置在电路板上。 电介质层形成在电路板上以覆盖电气设备，电极和第一导电图案，其中通过第一导电图案在电介质层中形成第一凹陷图案。 图案化电介质层以形成与通孔连接并暴露电极的通孔和第二凹陷图案。 导电材料填充在通孔和第二凹陷图案中以在通孔中形成导电通孔，并且在第二凹陷图案中填充第二导电图案。 去除衬底。 此外，还提供了电气装置封装结构。
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公开(公告)号：US20240282687A1
公开(公告)日：2024-08-22
申请号：US18650005
申请日：2024-04-29
Applicant: Unimicron Technology Corp.
Inventor： Chih-Chiang Lu , Hsin-Ning Liu , Jun-Rui Huang , Pei-Wei Wang , Ching Sheng Chen , Shih-Lian Cheng
CPC classification number: H01L23/49827 , H01L21/4857 , H01L21/486 , H01L23/49822 , H05K1/0222 , H05K3/0094 , H05K3/429 , H05K3/4614 , H05K3/4623 , H01L24/16 , H01L2224/16227 , H05K2201/09509 , H05K2201/0959
Abstract: A manufacturing method of the circuit board includes the following steps. A metal layer, a first substrate, a second substrate, and a third substrate are laminated. Multiple blind holes and a through hole are formed. A conductive material layer is formed, which covers the metal layer, the conductive layer of the third substrate, and an inner wall of the through hole, and fills the blind holes to define multiple conductive holes. The conductive material layer, the metal layer, and the conductive layer are patterned to form a first external circuit layer located on the first substrate and electrically connected to the conductive pillars, and a second external circuit layer located on the insulating layer and electrically connected to the conductive holes, and define a conductive through hole structure connecting the first external circuit layer and the second external circuit layer and located in the through hole.
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公开(公告)号：US12052815B2
公开(公告)日：2024-07-30
申请号：US18447265
申请日：2023-08-09
Applicant: Unimicron Technology Corp.
Inventor： Chih-Chiang Lu , Heng-Ming Nien , Ching-Sheng Chen , Ching Chang , Ming-Ting Chang , Chi-Min Chang , Shao-Chien Lee , Jun-Rui Huang , Shih-Lian Cheng
CPC classification number: H05K1/0222 , H05K1/113 , H05K1/119 , H05K3/429 , H05K3/462 , H05K1/181 , H05K3/0094 , H05K3/24 , H05K2201/10734
Abstract: Provided is a manufacturing method of circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The third substrate has an opening and includes a first dielectric layer. The opening penetrates the third substrate, and the first dielectric layer fills the opening. Multiple conductive structures are formed so that the first substrate, the second substrate, the third substrate, and the fourth substrate are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate. The conductive via structure is electrically connected to the first substrate and the fourth substrate to define a signal path, and the ground path surrounds the signal path.
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