公开(公告)号：JP2000174022A

公开(公告)日：2000-06-23

申请号：JP34587998

申请日：1998-12-04

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN KATEI ,  O SHITETSU

IPC: H01L21/3205 ,  H01L21/28 ,  H01L23/544

Abstract: PROBLEM TO BE SOLVED: To form an alignment mark of good functional quality for fully utilizing alignment performance by forming a metallic wiring layer, having openings for the mark with a higher step height. SOLUTION: A polysilicon layer 302 is formed on a semiconductor substrate, and a central part of the polysilicon layer is removed to cause the substrate to be exposed. An oxide layer 306 is then formed on the substrate and is patterned to form openings 308 to expose the substrate. A W (tungsten) layer 314 is deposited on the substrate and is flattened with a WCMP (tungsten chemical-mechanical polishing) process to form W plugs 312 in the openings. A metallic wiring layer is formed on the substrate. Finally, an alignment mark pattern is formed in the metallic wiring layer.

公开(公告)号：JP2000058828A

公开(公告)日：2000-02-25

申请号：JP26791898

申请日：1998-09-22

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUKIN ,  RO GYOREI ,  YEW TRI-RUNG

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide metallic silicide and a method for forming it. SOLUTION: In a silicon substrate 20, a field separation part is given and MOS containing a gate 22, spacers 25 on the side walls of the gate 22, and source/drain areas 24 is installed. A titanium layer 28 is formed on the silicon substrate 20. A first speedy thermal treatment is executed and the titanium layer 28 changes into titanium silicide in a first form. The titanium layer which is not changed into titanium silicide is removed. A high compressible film is formed on the silicon substrate 20. A second speedy thermal treatment is executed and a titanium silicide layer changes to a second form.

公开(公告)号：JP2000036541A

公开(公告)日：2000-02-02

申请号：JP28135498

申请日：1998-10-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHA CHOKEI ,  WOO SHUNGEN ,  RO KATETSU

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285

Abstract: PROBLEM TO BE SOLVED: To prevent a deviation or the like of a pattern in a photolithography or the like by vapor-depositing an intermetallic dielectric layer, patterning a via hole, then forming a titanium layer on the dielectric layer to connect a first aluminum layer formed in the hole, and forming a second aluminum layer on the titanium layer. SOLUTION: A first metal layer 202 is formed on a substrate 200, and then an intermetallic dielectric layer 204 is vapor deposited on the substrate 200 via a CVD. Then, the layer 204 is etched by using a photoresist pattern until a surface of the layer 202 is exposed to form a via hole 208. a second aluminum layer 211 is vapor deposited in the hole 208, and an aluminum via hole 213 is formed. Thereafter, a titanium layer 214 is formed on the layer 204 and the hole 213 by a physical vapor deposition method. A second aluminum layer 216 is formed on the layer 214 by using a physical vapor deposition method.

公开(公告)号：JP2000021879A

公开(公告)日：2000-01-21

申请号：JP31315898

申请日：1998-11-04

Applicant: UNITED MICROELECTRONICS CORP

Inventor： HUANG YIMIN ,  YANG MING-SHENG ,  YEW TRI-RUNG

IPC: H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To avoid excessively polishing a metal line which would increase the resistance of metal lines and the parasitic capacitance between conductor lines by forming a double waveform pattern, using shallow dummy metal lines. SOLUTION: A thin adhesive layer 328 is formed in shallow metal line trenches and on the surface of an inter-metal dielectric layer 317 along the side walls and bottoms of second metal line trenches, vias, and third metal line trenches, a metal layer and adhesive layer 328 located higher than the inter-metal dielectric layer 317 are polished by the chemical-mechanical polishing to result in that metal layer filled in the second metal line trenches, third metal line trenches 326 and shallow dummy metal line trenches have the same height as the inter-metal dielectric layer 317, thereby avoiding excessively polishing the metal lines which would increase the resistance and hence the operation speed of the device not becomes low because of a small parasitic capacitance.

公开(公告)号：JP2000019714A

公开(公告)日：2000-01-21

申请号：JP25786098

申请日：1998-09-11

Applicant: UNITED MICROELECTRONICS CORP

Inventor： BENJAMIN ZU MIN RIN

IPC: H01L21/027 ,  G03F1/32 ,  G03F1/42 ,  G03F1/68 ,  G03F9/00 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To provide a phase shift mask capable of performing accurate mask alignment. SOLUTION: A phase shift mask for shifting a phase has a transparent substrate having a first surface and second surface, a first pattern layer provided on the first surface of the transparent substrate for forming a mark pattern for aligning the phase shift mask by exposing a part of the first surface, and a second pattern layer provided on the second surface of the transparent substrate for covering the mark pattern so as to cover rays of light passing through the mark pattern by forming a hole pattern for manufacture by exposing a part of the second surface. Preferably, the transparent substrate has quartz or glass. The first pattern layer has a material that cuts off light, such as chromium. The second pattern layer has a material capable of shifting the phase of light, for example, by 180 degrees. The second pattern layer has transmissivity of about 3% to 10% while a pattern of the second pattern layer is being changed, and has transmissivity of about 50% while the phase shift mask is being aligned.

公开(公告)号：JPH11330077A

公开(公告)日：1999-11-30

申请号：JP18624498

申请日：1998-07-01

Applicant: UNITED MICROELECTRONICS CORP

Inventor： TSAI MENG JIN

IPC: H01L21/302 ,  H01L21/027 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide, in a simple process, dual damasking technology for forming dual damask structure without the occurrence of misalignments. SOLUTION: The forming technology of dual damask structure contains a process for forming an oxide layer 56 and a mask layer 58 on the oxide layer 56. The oxide layer 56 and the mask layer 58 have projections 57 positioned above first conduction layers 54. Chemical-mechanical polishing is executed, and the projections are removed. Then, an opening 59 is formed. A second conductive layer 68 is formed in the opening 59, and the second conductive layer 68 is brought into contact with the first conductive layer 54.

公开(公告)号：JP2945646B2

公开(公告)日：1999-09-06

申请号：JP1051198

申请日：1998-01-22

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI ,  SHIH HSUEH-HAO

IPC: C23C16/04 ,  C23C16/24 ,  H01L21/02 ,  H01L21/205 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：JPH11220097A

公开(公告)日：1999-08-10

申请号：JP32639898

申请日：1998-11-17

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHAO FANG-CHING ,  SHA BUNEKI ,  KO KOKUTAI

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a capacitor in a dynamic RAM, by changing a first tantalum oxide layer to a first acid tantalum nitride layer due to RTA treatment, and by forming a second acid tantalum nitride layer being formed on the first tantalum nitride layer on a second tantalum oxide layer. SOLUTION: A first tantalum oxide layer is formed on a polysilicon layer 30 being used as a lower electrode, first rapid thermal anneal treatment is made in ammonia atmosphere, and a first tantalum nitride layer 32a is formed by the reaction between the first tantalum oxide layer and ammonium. A second tantalum oxide layer is formed on a first acid tantalum nitride layer 32a, second rapid thermal anneal treatment is executed in dinitrogen monoxide atmosphere to rearrange the atom of a second tantalum oxide layer, third rapid thermal anneal treatment is executed in the ammonium atmosphere, and second tantalum nitride 36 is formed on the second tantalum oxide layer. After that, an upper electrode 38 is formed on the acid tantalum nitride layer 36.

公开(公告)号：JPH11191623A

公开(公告)日：1999-07-13

申请号：JP9206298

申请日：1998-04-03

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To manufacture a semiconductor device in an integrated process for making a self-aligned borderless contact of the element and a self-aligned local interconnection of the element. SOLUTION: A substrate 30 having a plurality of shallow trench insulating layers 31 is formed, first and second gate electrodes are respectively formed on a locally interconnected region 9" and an active region 9', source and drain regions 36 are formed through ion-implantation in the substrate 30 with the use of these first and second gate electrodes as masks, first spacers 37a, 37b and second spacers 37c, 37d are respectively formed at the peripheries first, and the second gate electrodes and the exposed parts of gate oxide films are removed. Self-aligned silicide films 42a to 42c are respectively formed on the surfaces of the regions 36, second insulating layers are formed, dielectric layers 35a,... are respectively formed on the second insulating layers and for making a self-aligned borderless contact and making a self-aligned local interconnection, a first opening is equipped on the region 9" and a second opening is equipped on the region 9'.

公开(公告)号：JPH11186404A

公开(公告)日：1999-07-09

申请号：JP35278697

申请日：1997-12-22

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To miniaturize an FET by selectively operating proper ion implantation to an active device area. SOLUTION: A device insulating part 32 is formed by an LOCOS method on a substrate 30, and the upper face is covered with a thick dialectic layer. Next, a gate electrode part 48 is etched, and a gate oxide layer 44 is formed at a substrate exposed part on the bottom face. Then, a channel part is formed by proper ion implantation through a gate electrode opening 48, and polysilicon is accumulated so that a gate electrode 48 can be formed. The thick dielectric layer is removed, a source/drain area 50 is doping formed, and an oxidized spacer 52 is formed at the gate electrode side face by CVD.