公开(公告)号：KR1020140000365A

公开(公告)日：2014-01-03

申请号：KR1020120067091

申请日：2012-06-22

Applicant: 한국과학기술원

Inventor： 류승탁 ,  오길근

IPC: H03M1/12

CPC classification number: H03M1/361 ,  H03M1/002 ,  H03M1/127 ,  H03M1/129 ,  H03M1/14 ,  H03M2201/2216 ,  H03M2201/62 ,  H03M2201/76

Abstract: The present invention relates to a pipeline analog to digital converter (ADC) comprising: an ADC module including N (N is natural number) sub modules discriminating analog input signals according to signal size intervals and performing digital conversion, and making some of the sub modules amplify a residual voltage to a range larger than an amplitude range of the analog input signals and transfer the amplified voltage to the next sub module; a clock signal generator for providing clock signals for the digital conversion to the N ADC modules; and a digital correction circuit for receiving the digital signal from the N ADC modules, correcting the received digital signal, and outputting the digital signal with M (M is natural number) bits.

Abstract translation: 本发明涉及一种流水线模数转换器（ADC），包括：包括N（N为自然数）子模块的ADC模块，根据信号尺寸间隔区分模拟输入信号并执行数字转换，并使一些子模块 将残余电压放大到大于模拟输入信号的幅度范围的范围，并将放大的电压传送到下一个子模块; 时钟信号发生器，用于向N个ADC模块提供数字转换的时钟信号; 以及数字校正电路，用于从N个ADC模块接收数字信号，校正接收到的数字信号，并以M（M为自然数）位输出数字信号。

公开(公告)号：KR101291341B1

公开(公告)日：2013-07-30

申请号：KR1020130001713

申请日：2013-01-07

Applicant: 주식회사 하이드로넷

Inventor： 임우석 ,  김상훈 ,  이준형

IPC: H03M1/12

CPC classification number: H03M1/20 ,  H03M1/123 ,  H03M1/361 ,  H03M2201/194 ,  H03M2201/2216 ,  H03M2201/6185 ,  H03M2201/625

Abstract: PURPOSE: A resolution improving device and a method thereof using an analog to digital converter port inside a MCU are provided to improve the resolution of an analog signals inputted from outside. CONSTITUTION: A resolution improving device of an analog to digital converter (ADC) comprises a bisectional unit (110), an adding device (120), and a MCU (130). The bisectional part divides an analog input signal into 2 halves for outputting the signal of a sub part. The adding device adds the analog input signal to the signal of the sub part which is outputted from the bisectional part for outputting. The MCU receives the analog input signal through a first ADC port and receives the main part signal of the signal divided into 2 halves through a second ADC port or an input and output port. The MCU converts the main part signal into a digital signal when a signal is inputted through the input and output port and assigns 1 to an additional bit above the most significant bit for outputting. The MCU converts the analog signal into the digital signal when a signal is not inputted through the input and output port and assigns 0 to the additional bit above the most significant bit for outputting. [Reference numerals] (110) Bisection of a signal; (120) Adding device; (AA) Input signal; (BB) Upper signal of the bisectional signal

Abstract translation: 目的：提供一种分辨率改进装置及其在MCU内使用模数转换器端口的方法，以提高从外部输入的模拟信号的分辨率。 构成：模数转换器（ADC）的分辨率改善装置包括二分单元（110），加法装置（120）和MCU（130）。 二等分部分将模拟输入信号分成两半，用于输出子部分的信号。 添加装置将模拟输入信号添加到从二分割部分输出的子部分的信号以进行输出。 MCU通过第一个ADC端口接收模拟输入信号，并通过第二个ADC端口或输入和输出端口将信号的主要部分信号分为两半。 当通过输入和输出端口输入信号时，MCU将主要部分信号转换为数字信号，并将1分配给高于最高有效位以用于输出。 当信号不通过输入和输出端口输入时，MCU将模拟信号转换为数字信号，并将0分配给最高有效位以上的附加位进行输出。 （附图标记）（110）信号的二等分; （120）添加设备; （AA）输入信号; （BB）二分信号的上位信号

公开(公告)号：KR101160962B1

公开(公告)日：2012-06-29

申请号：KR1020110040171

申请日：2011-04-28

Applicant: 서강대학교산학협력단

Inventor： 이승훈 ,  구병우 ,  박혜림

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/0607 ,  H03M1/361 ,  H03M2201/2216 ,  H03M2201/61 ,  H03M2201/622 ,  H03M2201/643

Abstract: PURPOSE: An ADC(Analog To Digital Converter) for processing wideband variable input signals is provided to adopt all WUXGA(Wide Ultra Extended Graphics Array) resolutions from VGA(Video Graphics Array) by applying a second stage reference voltage selection method to a flash ADC. CONSTITUTION: A SHA(Sample-And-Hold Amplifier)(110) exactly samples values which are suitable for necessary specification by using GBC(Gate-Bootstrapping Circuit). A MDAC(Multiplying Digital-To-Analog Converter)(120) reduces the necessary number of unit capacitors by half since a merged-capacitor switching technique is applied. A FLASH1 ADC(Analog To Digital Converter)(130) and a FLASH2 ADC(140) apply an interpolation method. An on-chip reference current voltage generator(150) processes a broadband variable input signal through one external signal. A clock generator(160) generates non-overlapped two clocks from one reference clock, which is inputted from the outside, in a chip. A digital correction circuit(170) including the clock generator and a divider is integrated with an on-chip.

Abstract translation: 目的：提供用于处理宽带可变输入信号的ADC（模/数转换器），以通过将第二级参考电压选择方法应用于闪存ADC来采用VGA（视频图形阵列）中的所有WUXGA（Wide Ultra Extended Graphics Array） 。 构成：SHA（采样保持放大器）（110）通过使用GBC（栅极引导电路）精确地采样适合于必要规格的值。 使用合并电容切换技术，MDAC（乘法数模转换器）（120）将必需数量的单位电容器减少了一半。 FLASH1 ADC（模数转换器）（130）和FLASH2 ADC（140）应用插值方法。 片上参考电流电压发生器（150）通过一个外部信号处理宽带可变输入信号。 时钟发生器（160）从芯片中从外部输入的一个参考时钟产生非重叠的两个时钟。 包括时钟发生器和分频器的数字校正电路（170）与片上集成。

公开(公告)号：KR1020070076111A

公开(公告)日：2007-07-24

申请号：KR1020060005123

申请日：2006-01-17

Applicant: 엘지전자 주식회사

Inventor： 김세원 ,  김상진

IPC: H03M1/12

CPC classification number: H03M1/203 ,  H03M1/123 ,  H03M2201/1172 ,  H03M2201/2216 ,  H03M2201/6185 ,  H03M2201/625

Abstract: A multi channel analog-digital converting apparatus is provided to reduce the size of apparatus and cost by forming a channel group composed of a sampling switch with low resolution and a channel group composed of a sampling switch with high resolution. A multi channel analog-digital converting apparatus includes a first channel group(10), a second channel group(20), and a group sampling switch(30). The first channel group(10) is composed of sampling switches of a predetermined number of channels having first resolution. The second channel group(20) is composed of sampling switches of a predetermined number of channels having second resolution. One side of the group sampling switch(30) is connected with the output of the second channel group(20), and the other side thereof is connected with the output of the first channel group(10).

Abstract translation: 提供一种多通道模拟数字转换装置，通过形成由低分辨率的采样开关构成的通道组和由高分辨率的采样开关组成的通道组来减小设备的尺寸和成本。 多通道模拟数字转换装置包括第一通道组（10），第二通道组（20）和组采样开关（30）。 第一通道组（10）由具有第一分辨率的预定数量的通道的采样开关组成。 第二通道组（20）由具有第二分辨率的预定数量的通道的采样开关组成。 组采样开关（30）的一侧与第二通道组（20）的输出端连接，另一侧与第一通道组（10）的输出端连接。

公开(公告)号：KR1020070030002A

公开(公告)日：2007-03-15

申请号：KR1020050084721

申请日：2005-09-12

Applicant: 엘지전자 주식회사

Inventor： 도형욱

IPC: H03M1/12 ,  H03M1/36

CPC classification number: H03M1/36 ,  H03M1/1205 ,  H03M2201/2216 ,  H03M2201/62

Abstract: A high efficiency analog-digital converter is provided to reduce a size of the whole chip in the converter by reducing the number of capacitor arrays which perform a bit conversion by charging a voltage in the analog-digital converter. A high efficiency analog-digital converter includes a charging/discharging circuit, a voltage recording circuit(10), and a voltage switch circuit(SR1,SR2,SR3). The charging/discharging circuit has five capacitors and five charge switches which are connected to an input terminal of a comparator(COM2) in parallel. The voltage recording circuit(10) stores a voltage charged in the charging/discharging circuit every upper four bit and lower four bit. The voltage switch circuit(SR1,SR2,SR3) performs switching for bit conversion of the upper four bit and the lower four bit.

Abstract translation: 提供了一种高效率模数转换器，通过减少通过对模拟数字转换器中的电压进行充电来执行位转换的电容器阵列的数量来减小转换器中整个芯片的尺寸。 高效率模拟数字转换器包括充电/放电电路，电压记录电路（10）和电压开关电路（SR1，SR2，SR3）。 充电/放电电路具有并联连接到比较器（COM2）的输入端的五个电容器和五个充电开关。 电压记录电路（10）存储充电/放电电路中每4位高4位的电压。 电压开关电路（SR1，SR2，SR3）执行上四位和下四位的位转换的切换。

公开(公告)号：KR1020120122972A

公开(公告)日：2012-11-07

申请号：KR1020120044826

申请日：2012-04-27

Applicant: 인터실 아메리카스 엘엘씨

Inventor： 키담비,선더에스.

IPC: H03M1/12

CPC classification number: H03M1/1215 ,  H03M1/0607 ,  H03M1/1245 ,  H03M2201/2216 ,  H03M2201/23 ,  H03M2201/6107 ,  H03M2201/6309

Abstract: PURPOSE: A gradient-based approach to sample-time mismatch error calibration in a two-channel time-interleaved analog-to-digital converter is provided to correct a phase error at a 2-channel TIADC(time interleaved analog to digital converter) system which is independent from a Nyquist zone. CONSTITUTION: An input signal is converted into first and second digital signals in order to provide two sets of ADC outputs. A sample time error is estimated from the first and second digital signals. A correction signal is determined from a sample time error regardless of a Nyquist zone which is occupied by an input signal. The correction signal is applied to the converting step. The step of determining the correction signal includes a step of estimating a gradient of the sample time error. [Reference numerals] (AA) Size(db); (BB) Input signal spectrum in a first Nyquist zone

Abstract translation: 目的：提供两通道时间交织模数转换器中采样时间失配误差校准的基于梯度的方法，以纠正2通道TIADC（时间交错模数转换器）系统的相位误差 它独立于奈奎斯特地带。 构成：输入信号转换为第一和第二数字信号，以提供两组ADC输出。 从第一和第二数字信号估计采样时间误差。 无论与输入信号占据的奈奎斯特区域无关，都从采样时间误差确定校正信号。 校正信号被应用于转换步骤。 确定校正信号的步骤包括估计采样时间误差的梯度的步骤。 （标号）（AA）尺寸（db）; （BB）第一奈奎斯特区域中的输入信号频谱

公开(公告)号：KR1020120015155A

公开(公告)日：2012-02-21

申请号：KR1020100077436

申请日：2010-08-11

Applicant: 정태경

Inventor： 정태경 ,  백승현

IPC: H03M1/12

CPC classification number: H03M1/361 ,  H03M1/002 ,  H03M1/1205 ,  H03M2201/2216 ,  H03M2201/2291 ,  H03M2201/62

Abstract: PURPOSE: A structure and method of circuit design for implementing low power consumption and a minimum area for a flash analog to digital converter are provided to simplify the structure of a convertor for low power consumption by reducing the number of repeated elements. CONSTITUTION: An analog to digital converter(100) includes a FDBD(First maximum bit determination) unit(110) and a SCTH(Signal Conversion to Half Signal) unit(120) The converter comprises a buffer(111), a resistance ladder(130), an amplification and comparison unit(140), an encoder(150), and XNOR(Exclusive NOR) logic unit(160). The FDBD unit outputs a corresponding signal by determining a MSB(Most Significant Bit) value. The SCTHO unit generates an absolute value signal(Vsmall) about the difference between an input analog signal and a 1/2 of a voltage. A whole circuit size and power consumption shrink by reducing the complex elements of the resistance ladder, the amplification and comparison unit, and the encoder.

Abstract translation: 目的：提供用于实现低功耗和闪存模数转换器的最小面积的电路设计的结构和方法，以通过减少重复元件的数量来简化用于低功耗的转换器的结构。 构成：模数转换器（100）包括FDBD（第一最大位确定）单元（110）和SCTH（信号转换为半信号）单元（120）。转换器包括缓冲器（111），电阻梯（ 130），放大和比较单元（140），编码器（150）和XNOR（异或逻辑）逻辑单元（160）。 FDBD单元通过确定MSB（最高有效位）值来输出相应的信号。 SCTHO单元产生关于输入模拟信号和电压的1/2之间的差的绝对值信号（Vsmall）。 通过减少电阻梯，放大和比较单元以及编码器的复杂元件，可以缩小整个电路尺寸和功耗。

公开(公告)号：KR1020110090669A

公开(公告)日：2011-08-10

申请号：KR1020100010598

申请日：2010-02-04

Applicant: 건국대학교 산학협력단 ,  광운대학교 산학협력단

Inventor： 이강윤 ,  민경직 ,  김주성

IPC: H03M1/38 ,  H03M1/12

CPC classification number: H03M1/46 ,  H03M1/002 ,  H03M1/361 ,  H03M2201/2216 ,  H03M2201/2233 ,  H03M2201/62

Abstract: PURPOSE: An ADC(Analog to Digital Converter) with a successive approximation register is provided to reduce a design area by simply changing the structure of an analog to digital converter with a SAR(Successive Approximation Register). CONSTITUTION: A reference unit(100) generates the reference voltage of a conversion section. A timing unit(500) generates the reference time for the total conversion process of an analog input signal. A digital error correction unit(600) mixes conversion codes in a digital part based on the reference generated in the timing unit. The digital error correction unit generates the digital total conversion codes of the analog input signal. The conversion codes in a digital part are generated in a first flash ADC(ANALOG TO DIGITAL CONVERTER,200) and a second flash ADC(300).

Abstract translation: 目的：提供具有逐次逼近寄存器的ADC（模数转换器），通过简单地通过SAR（连续逼近寄存器）改变模数转换器的结构来减少设计区域。 构成：参考单元（100）产生转换部分的参考电压。 定时单元（500）产生模拟输入信号的总转换处理的基准时间。 数字纠错单元（600）基于在定时单元中生成的参考来混合数字部分中的转换代码。 数字纠错单元产生模拟输入信号的数字总转换代码。 数字部分中的转换代码在第一闪存ADC（模拟到数字转换器，200）和第二闪存ADC（300）中生成。

公开(公告)号：KR1020110040061A

公开(公告)日：2011-04-20

申请号：KR1020090097187

申请日：2009-10-13

Applicant: 인하대학교 산학협력단

Inventor： 윤광섭 ,  김원

IPC: H03M1/12

CPC classification number: H03M1/362 ,  H03M1/002 ,  H03M1/1205 ,  H03M2201/2216

Abstract: PURPOSE: An analog-digital converter using a digital range detector circuit is provided to sense an input voltage range by using a digital range detector terminal circuit. CONSTITUTION: A voltage divider(100) divides a reference voltage by using a resistor. A range detection/clock divider(200) generates a clock signal within a corresponding range. A first shear amplifier(300) amplifies two differential reference voltages and two differential analog signals. A second shear amplifier(400) amplifies two output signals from the first shear amplifier. A comparator(600) synchronizes two amplification signals based on a clock source. A bubble error corrector(700) corrects a bubble error generated in a comparator. An encoder(800) converts the corrected output signal to a digital code. A synchronization unit(900) synchronizes the output signal of the encoder according to a main clock signal.

Abstract translation: 目的：提供使用数字量程检测器电路的模拟数字转换器，通过使用数字量程检测器端子电路来检测输入电压范围。 构成：分压器（100）使用电阻对参考电压进行分压。 范围检测/时钟分频器（200）产生相应范围内的时钟信号。 第一剪切放大器（300）放大两个差分参考电压和两个差分模拟信号。 第二剪切放大器（400）放大来自第一剪切放大器的两个输出信号。 比较器（600）基于时钟源同步两个放大信号。 气泡误差校正器（700）校正比较器中产生的气泡误差。 编码器（800）将校正的输出信号转换成数字码。 同步单元（900）根据主时钟信号同步编码器的输出信号。

公开(公告)号：KR20100081476A

公开(公告)日：2010-07-15

申请号：KR20090000732

申请日：2009-01-06

Applicant: HYNIX SEMICONDUCTOR INC ,  IUCF HYU

Inventor： GOU JA SEUNG ,  KWON OH KYONG ,  SHIN MIN SEOK ,  KIM MIN KYU

IPC: H03M1/12 ,  H03M1/66

CPC classification number: H03M1/14 ,  H03M1/122 ,  H03M1/361 ,  H03M1/662 ,  H03M2201/2216 ,  H03M2201/62

Abstract: PURPOSE: A pipeline ADC is provided to reduce power consumption by reducing the number of a MDAC(Multiplying Digital to Analog Converter). CONSTITUTION: A calculation amplifier(350) interlinks a positive input end to the ground. A first channel(360) is formed between the output end of a calculation amplifier and a negative input end. A second channel(370) is formed between the output end and a sub input end. An input selection part(380) determines a first channel, a second channel, a connection state between an analog signal input end and a reference voltage input end. A control signal supplying part(390) controls a first channel, a second channel, the connected state of the input selection part.

Abstract translation: 目的：提供流水线ADC，通过减少MDAC（乘数数模转换器）的数量来降低功耗。 构成：计算放大器（350）将正输入端与地相互连接。 第一通道（360）形成在计算放大器的输出端和负输入端之间。 在输出端和子输入端之间形成第二通道（370）。 输入选择部分（380）确定第一通道，第二通道，模拟信号输入端和参考电压输入端之间的连接状态。 控制信号提供部分（390）控制第一通道，第二通道，输入选择部件的连接状态。