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公开(公告)号：KR1020060124326A
公开(公告)日：2006-12-05
申请号：KR1020050046192
申请日：2005-05-31
Applicant: 엘지전자 주식회사
Inventor： 이승현
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M7/165 , H03M2201/814 , H03M2201/93
Abstract: A digital to analog converter module is provided to reduce a manufacturing cost by forming an integrated structure as one chip. A thermometer decoder(110) converts an inputted upper digital code of m bits to a thermometer code. A latch unit(120) synchronizes the thermometer code and an inputted lower digital code of m bits according to an inputted clock signal. A thermometer code current cell matrix(160) is driven by the thermometer code outputted from the latch unit in order to convert the thermometer code to analog current. First and second binary weight current cells are driven by the lower digital code of m bits outputted from the latch unit in order to convert the lower digital code of m bits to the analog current. A switching unit(130) outputs selectively the lower digital code of m bits to the first binary weight current cell or the second binary weight current cell according to a mode selection signal.
Abstract translation: 提供了一种数模转换器模块，通过形成作为一个芯片的集成结构来降低制造成本。 温度计解码器（110）将输入的m位的上位数字码转换为温度计代码。 闩锁单元（120）根据输入的时钟信号使温度计代码和输入的m位的较低数字码同步。 温度计代码当前单元矩阵（160）由从锁存单元输出的温度计代码驱动，以将温度计代码转换为模拟电流。 第一和第二二进制加权电流单元由从锁存单元输出的m位的较低数字码驱动，以便将较低数字码的m位转换为模拟电流。 根据模式选择信号，切换单元（130）选择性地将m位的较低数字码输出到第一二进制加权当前单元或第二二进制加权当前单元。
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公开(公告)号：KR1020060098551A
公开(公告)日：2006-09-19
申请号：KR1020050017707
申请日：2005-03-03
Applicant: 엘지전자 주식회사
CPC classification number: H03M1/0863 , H03M1/742 , H03M2201/30 , H03M2201/6318 , H03M2201/644 , H03M2201/645 , H03M2201/814
Abstract: 본 발명은 커런트 스티어링 DAC의 단위 커런트 셀을 구동하기 위한 디글리치 회로에 있어서, 상기 디글리치 회로의 입력단에 구비되어, 입력단의 스위치의 온/오프에 따른 발생되는 챠지를 흡수하는 더미 스위치를 포함함을 특징으로 한다.
또한, 본 발명에서는 상기 디글리치 회로의 출력단에 버퍼부를 더 포함함을 특징으로 한다.
상기 더미 스위치는 캐패시터 또는 모스트랜지스터로 구현할 수 있다.
이상에서와 같이, 본 발명은 커런트 스티어링(Current steering) 구조의 DAC에서 커런트 셀(Current Cell)을 구동할 때, 스위치(Switch)의 온/오프(On/Off)로 발생하는 글리치 에너지(Glitch Energy)를 효과적으로 최소화하여 출력단에서 발생하는 글리치 에러(Glitch Error)를 줄여 DAC 출력의 선형성, 디퍼런셜 비 선형성(Differential Non-Linearity), 신호대잡음비(Signal-to-Noise Ratio)를 개선 시킬 수 있다.
커런트 스티어링 DAC, 디글리치, 더미 스위치-
公开(公告)号：KR1020030002464A
公开(公告)日：2003-01-09
申请号：KR1020010038081
申请日：2001-06-29
Applicant: 삼성전자주식회사
Inventor： 구형완
IPC: H03M1/66
CPC classification number: H03M1/742 , H03M2201/6372 , H03M2201/814
Abstract: PURPOSE: A current output type digital/analog converter is provided, which reduces a differential linearity of an output current value by increasing a channel width of a transistor included in a 16 times or 32 times current source. CONSTITUTION: According to a current output type digital/analog converter comprising units outputting current value respectively and being connected to a common port, each unit comprises the first and the second current sources(192,196) outputting an upper data bit group and including a plurality of serially connected transistors, and the third current source(194) outputting a lower data bit group and including at least one transistor. At least one of the transistors of the first and the second current source has a different channel width from other transistors.
Abstract translation: 目的：提供电流输出型数字/模拟转换器，通过增加包含在16倍或32倍电流源中的晶体管的沟道宽度来减小输出电流值的微分线性度。 构成：根据电流输出型数字/模拟转换器，其包括分别输出电流值并连接到公共端口的单元，每个单元包括第一和第二电流源（192,196），其输出上数据位组并且包括多个 串联连接的晶体管，第三电流源（194）输出下部数据位组并且包括至少一个晶体管。 第一和第二电流源的至少一个晶体管具有与其它晶体管不同的沟道宽度。
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公开(公告)号：KR1020020015770A
公开(公告)日：2002-03-02
申请号：KR1020000048873
申请日：2000-08-23
Applicant: 동부일렉트로닉스 주식회사 , 주시회사 골드퍼시픽
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/06 , H03M2201/61 , H03M2201/814
Abstract: PURPOSE: A digital analog converter is provided, which can reduce an INLE(Integral Non Linearity Error) and a DNLE(Differential Non Linearity Error) by making a current flowing from each MOS transistor to a switch of each unit current cell equal each other. CONSTITUTION: According to the digital analog converter, a decoder(100) decoding a digital input signal(DIG) is arranged on the left, and a current switch part(400) comprising unit current cells(SM11,SM12,..,SMni) in a matrix form constituted with a number of switches(S1,S2,...) outputting a current(IOUT) corresponding to the digital input signal is arranged on the right of the decoder. One end of each switch is connected to each drain port of a number of MOS transistors(M1,M2...Mi...). And a current supply MOS transistor(Ms)(300) of a mirror circuit constituted with a current supply MOS transistor(Ms) and a number of MOS transistors(M1,M2...Mi...) are arranged on an upper part of the current switch part, and each MOS transistor is arranged in the unit current cell. The current supply MOS transistor is connected to a constant current source(I0) supplying a constant current with a source port connected to a power supply voltage(Vdd).
Abstract translation: 目的：提供数字模拟转换器，通过使电流从每个MOS晶体管流向每个单元当前单元的开关相互相等，可以减少INLE（积分非线性误差）和DNLE（差分非线性误差）。 构成：根据数字模拟转换器，在左侧布置解码器（100），数字输入信号（DIG）进行解码，并且包括单位当前单元（SM11，SM12，...，SMni）的电流开关部分（400） 以与数字输入信号相对应的输出电流（IOUT）的多个开关（S1，S2，...）构成的矩阵形式配置在解码器的右侧。 每个开关的一端连接到多个MOS晶体管（M1，M2 ... Mi ...）的每个漏极端口。 并且，由电流源MOS晶体管（Ms）和多个MOS晶体管（M1，M2 ... Mi ...）构成的镜面电路的电流源MOS晶体管（Ms）（300）设置在上部 的电流开关部分，并且每个MOS晶体管布置在单位电流单元中。 电流源MOS晶体管连接到与连接到电源电压（Vdd）的源极端口提供恒定电流的恒流源（I0）。
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公开(公告)号：KR1020000014640A
公开(公告)日：2000-03-15
申请号：KR1019980034148
申请日：1998-08-22
Applicant: 현대반도체 주식회사
Inventor： 김지현
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/0818 , H03M1/0863 , H03M2201/644 , H03M2201/814
Abstract: PURPOSE: The converter is to minimize glitch which is occurred at a time of code-conversion by use of input decoder having high cross point to draw rapid setting time. CONSTITUTION: The converter comprises many decoders which receive digital signal by bit unit and decode it with short delay time to output first signal and second signal that are crossed each other at high voltage level, many switch current parts which receive the first signal and the second signal respectively from the decoders and generate a first and second switching current according to the received signals, and a current mirror which receives a first and a second switching current from many switch current parts, prevents change of signal due to a feed draw phenomenon as generated by the first and second switching current and mirrors it. Thus, stable output signal is obtained by preventing change of voltage between gate and source of MOS transistor which is generated due to the feed draw phenomenon by inputting decoded signal of switch current part.
Abstract translation: 目的：转换器通过使用具有高交叉点的输入解码器来最小化在代码转换时发生的毛刺，以绘制快速设置时间。 构成：转换器包括多个解码器，它们通过位单元接收数字信号，并以较短的延迟时间对其进行解码，以输出第一个信号，并在高电压电平下交叉彼此的第二个信号，许多接收第一个信号的开关电流部分和第二个信号 信号，并且根据接收到的信号产生第一和第二开关电流，以及从许多开关电流部分接收第一和第二开关电流的电流镜，防止由于产生的馈送汲取现象引起的信号变化 通过第一和第二开关电流并对其进行镜像。 因此，通过输入开关电流部分的解码信号，防止由于馈电现象而产生的MOS晶体管的栅极和源极之间的电压变化，从而获得稳定的输出信号。
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Patent Agency Ranking
公开(公告)号：KR101481151B1
公开(公告)日：2015-01-14
申请号：KR1020130114936
申请日：2013-09-27
Applicant: 동국대학교 산학협력단
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M2201/62 , H03M2201/814 , H03M2201/932
Abstract: 본 발명은 출력전압의 풀 스윙이 가능한 디지털 아날로그 변환기 및 변환방법에 관한 것으로서, 보다 구체적으로는 아날로그 형태로 변환하고자 하는 제1 디지털 신호를 출력하는 디지털 신호처리부; 출력된 상기 제1 디지털 신호를 입력받고, 상기 제1 디지털 신호에 응답하여 전류원이 포화영역에 도달하여 구동하도록 제어하는 복수 개의 제2 디지털 신호를 생성하여 출력하는 쿼터너리 드라이버; 상기 복수 개의 제2 디지털 신호를 입력받고, 상기 복수 개의 2 디지털 신호에 따라 포화영역에 도달하여 구동되어 출력전압별 아날로그 신호를 각각 출력하는 서로 다른 형태의 제1 전류원 내지 제2 전류원; 및 상기 제1 전류원 및 제2 전류원으로부터 출력된 각각의 아날로그 신호를 합성하여 최종 아날로그 신호를 생성한 후 출력하는 멀티플렉서;를 포함한다.
이러한 구성에 의해, 본 발명의 출력전압의 풀 스윙이 가능한 디지털 아날로그 변환기는 출력전압의 범위가 일정 부분만 해당하는 것이 아니라, 접지전압부터 전원전압의 레벨까지 풀 스윙이 가능하도록 함으로써, 디지털 신호에 대한 아날로그 신호로의 변환 성능을 향상시킬 수 있는 효과가 있다.Abstract translation: 本发明涉及具有输出电压全摆幅功能的数字模拟转换器（DAC）及其方法。 更具体地，DAC包括数字信号处理单元，用于输出要转换成模拟信号的第一数字信号; 四进制驱动器，用于接收输出的第一数字信号，并产生并输出多个第二数字信号，以响应于第一数字信号控制电流源驱动达到饱和区; 第一和第二电流源彼此不同以接收第二数字信号并根据要驱动的第二数字信号到达饱和区域，使得第一和第二电流源分别根据输出电压输出模拟信号; 以及多路复用器，用于组合从第一和第二电流源输出的模拟信号，并产生并输出最终的模拟信号。 通过上述结构，根据具有本发明的输出电压的全摆幅功能的DAC，仅输出电压范围的一部分不受全摆幅功能的影响，但是全摆幅功能被应用于所有范围 从地电压到电源电压。 因此，能够提高从数字信号向模拟信号的转换性能。
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公开(公告)号：KR1020100123103A
公开(公告)日：2010-11-24
申请号：KR1020090042136
申请日：2009-05-14
Applicant: 주식회사 실리콘웍스
CPC classification number: H03M1/66 , H03M1/06 , H03M2201/3194 , H03M2201/61 , H03M2201/62 , H03M2201/814
Abstract: PURPOSE: By it partials, medially eliminating error toward the input of digital data the digital to analog converter enhances the accuracy of the digital to analog converter. CONSTITUTION: It distributes to the before distribution class field of the plurality having the size of the reference current decision by discussion search the reference current which the electric current distribution part(20) is provided from the reference current route of supply source. According to the rotating exchange part is the control signal, the route of the before distribution class field having the route of being exchanged as described above is re-exchanged.
Abstract translation: 目的：通过内部消除数字数据输入的错误，数模转换器提高了数模转换器的精度。 构成：通过讨论从供应源的参考电流路径提供电流分配部（20）的参考电流，分配到具有参考电流决定大小的多个的前分发类场中。 根据旋转交换部分是控制信号，重新交换具有如上所述交换路线的分配前场的路线。
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公开(公告)号：KR1020100027278A
公开(公告)日：2010-03-11
申请号：KR1020080086126
申请日：2008-09-02
Applicant: 충북대학교 산학협력단
CPC classification number: H03M1/16 , H03M1/002 , H03M1/18 , H03M2201/62 , H03M2201/814
Abstract: PURPOSE: An analog to digital converter using threshold voltage variation is provided to simplify a configuration of a circuit by performing a comparison operation with a simple structure. CONSTITUTION: A switching inverter array(120) is comprised of a plurality of CMOS inverters. The switching inverter array receives an analog input voltage as an input signal. An encoder(150) generates a digital signal by encoding the output signals of the CMOS inverters. Each CMOS inverter has a different switching threshold voltage. The CMOS inverters is comprised of a PMOS transistor and an NMOS transistor including a gate insulation layer. The PMOS transistor and the NMOS transistor have different thicknesses according to each CMOS inverter.
Abstract translation: 目的：提供使用阈值电压变化的模数转换器，通过简单的结构执行比较操作来简化电路的配置。 构成：开关逆变器阵列（120）由多个CMOS反相器构成。 开关逆变器阵列接收模拟输入电压作为输入信号。 编码器（150）通过对CMOS反相器的输出信号进行编码来产生数字信号。 每个CMOS反相器具有不同的开关阈值电压。 CMOS反相器由PMOS晶体管和包括栅极绝缘层的NMOS晶体管组成。 根据每个CMOS反相器，PMOS晶体管和NMOS晶体管具有不同的厚度。
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公开(公告)号：KR1020090068796A
公开(公告)日：2009-06-29
申请号：KR1020070136555
申请日：2007-12-24
Applicant: 주식회사 디비하이텍
Inventor： 김일곤
CPC classification number: H03M7/16 , H01L27/0922 , H03M7/005 , H03M2201/814
Abstract: A semiconductor circuit device and a code converting device are provided to synchronize data processing with a clock of a system configured by hardware, thereby preventing error during data processing. A code converting device(130) converts a gray code latched in the first to fourth input latches into a binary code. A clock generator provides a clock to the first to fourth input latches through a metal line. The first to fourth output latches latch a binary code value received in the code converting device.
Abstract translation: 提供半导体电路装置和代码转换装置，以使数据处理与由硬件配置的系统的时钟同步，从而防止数据处理期间的错误。 代码转换装置（130）将在第一至第四输入锁存器中锁存的灰色代码转换为二进制代码。 时钟发生器通过金属线向第一至第四输入锁存器提供时钟。 第一至第四输出锁存器锁存在代码转换装置中接收的二进制代码值。
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公开(公告)号：KR1020080091536A
公开(公告)日：2008-10-14
申请号：KR1020070034492
申请日：2007-04-09
Applicant: 인하대학교 산학협력단
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/06 , H03M2201/62 , H03M2201/814 , H03M2201/932
Abstract: A DAC using partial randomization is provided to increase an operation speed of the DAC by reducing glitch energy by randomly selecting a current source and a significant data signal line. A DAC(Digital to Analog Converter) includes plural decoding layers having respective current sources. When the current source is randomly selected, glitch energy is decreased. The number of layers is determined for a layout size of the DAC and the reduction of the glitch energy. The number of layers is optimized according to the bit number of the DAC, so that the linearity of the DAC is guaranteed. Random signals required for the respective layers are obtained from a linear feedback shift register(LFSR).
Abstract translation: 提供使用部分随机化的DAC以通过随机选择电流源和有效数据信号线来减少毛刺能量来增加DAC的操作速度。 DAC（数模转换器）包括具有各自电流源的多个解码层。 当电流源随机选择时，毛刺能量下降。 针对DAC的布局尺寸和毛刺能量的减少确定层数。 根据DAC的位数优化层数，从而保证DAC的线性度。 从线性反馈移位寄存器（LFSR）获得各层所需的随机信号。
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