公开(公告)号：KR1020130063175A

公开(公告)日：2013-06-14

申请号：KR1020110129558

申请日：2011-12-06

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 선민철 ,  박병국

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/0673 ,  H01L29/7854 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/772

Abstract: PURPOSE: A field effect transistor having a back-gate and a method for forming the same are provided to effetely restrain an off-state leakage current and to secure a semiconductor device having excellent electrical properties. CONSTITUTION: A back-bias region(37) is formed on a substrate(11). A filling isolation layer(15) covers the substrate and the back-bias region. A body is partly overlapped with the back-bias region. A drain(47) is contacted with the body. A gate electrode(25) covers the upper and the lateral surface of the body.

Abstract translation: 目的：提供具有背栅的场效应晶体管及其形成方法，以有效地抑制截止状态的漏电流并确保具有优异电性能的半导体器件。 构成：在衬底（11）上形成背偏置区（37）。 填充隔离层（15）覆盖基板和背偏置区域。 身体部分地与背偏置区域重叠。 排水口（47）与身体接触。 栅电极（25）覆盖主体的上表面和侧表面。

公开(公告)号：KR1020120049720A

公开(公告)日：2012-05-17

申请号：KR1020100111121

申请日：2010-11-09

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 권대웅 ,  박병국 ,  김창정 ,  박재철

IPC: G09G3/30

CPC classification number: G09G3/3233 ,  G09G2300/0842 ,  G09G2310/0251 ,  G09G3/30 ,  G09G3/32

Abstract: PURPOSE: A driving method of an active type display device is provided to recover threshold voltage of a thin film transistor by applying negative bias voltage to a drain electrode of a switching transistor. CONSTITUTION: A switching transistor is connected to a pixel. Negative bias voltage is applied to the switching transistor. The negative bias voltage is applied before charging each pixel. Threshold voltage of the switching transistor is recovered. The negative bias voltage is applied to a drain electrode of the switching transistor.

Abstract translation: 目的：提供一种有源型显示装置的驱动方法，通过向开关晶体管的漏极施加负偏置电压来恢复薄膜晶体管的阈值电压。 构成：开关晶体管连接到像素。 负偏置电压施加到开关晶体管。 在对每个像素充电之前施加负偏压。 恢复开关晶体管的阈值电压。 负偏压施加到开关晶体管的漏电极。

公开(公告)号：KR1020110081623A

公开(公告)日：2011-07-14

申请号：KR1020100001878

申请日：2010-01-08

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 오정훈 ,  유경창 ,  박병국 ,  오경석 ,  백인규

IPC: G11C16/00 ,  G11C16/30 ,  G11C11/21

CPC classification number: G11C13/0002 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/102 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: PURPOSE: A semiconductor devices and a method of driving the same are provided to implement high integration by preventing the interference between nonvolatile memory cells. CONSTITUTION: In a semiconductor devices and a method of driving the same, a unit cell structure(1) comprises electrode layers(M1,M2), a bipolar resistance memory material film(RM1), and a unipolar resistance memory material film(RM2) The bipolar resistance memory material film and the unipolar resistance memory material film are formed between electrode layers which are opposite to each other. The bipolar resistance memory material film and the unipolar resistance memory material film are electrically serially connected. The electrode layers include resistance memory material films which are connected to conductive lines respectively.

Abstract translation: 目的：提供半导体器件及其驱动方法，以通过防止非易失性存储单元之间的干扰来实现高集成度。 构成：在半导体器件及其驱动方法中，单元电池结构（1）包括电极层（M1，M2），双极性电阻记忆材料膜（RM1）和单极电阻存储材料膜（RM2） 双极性电阻记忆材料膜和单极电阻记忆材料膜形成在彼此相对的电极层之间。 双极性电阻记忆材料膜和单极性电阻记忆材料膜电连接。 电极层包括分别连接到导线的电阻记忆材料膜。

公开(公告)号：KR1020080051014A

公开(公告)日：2008-06-10

申请号：KR1020070095665

申请日：2007-09-20

Applicant: 삼성전자주식회사

Inventor： 박병국 ,  박일한 ,  채수두 ,  김정우 ,  한정희 ,  박찬진

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L27/2481

Abstract: An AND-type and NOR-type flash memory arrays, a manufacturing method thereof and an operating method thereof are provided to form plural same silicon pins having certain width and height on an upper portion of a substrate. A local bit line(LBL1) is connected to bit lines(BL1,BL2,BLn) via a first select transistor(ST11). Memory cells(M11 to Mm1) are connected in parallel to the local bit line and the local source line. A local source line(LSL1) is commonly connected to a source of the respective memory cells, and a common source line(CSL) is connected to the local source line via a second select transistor(ST21). A drain select line(DSL) and a source select line(SSL) are electrically connected to a gate of the first select transistor and a gate of the second select transistor. Plural word lines(WL1 to WLm) are connected to a gate of each memory cell. The local bit line and the local source line have a first doped layer and a second doped layer which are vertically spaced apart from silicon pins.

Abstract translation: 提供AND型和NOR型闪速存储器阵列，其制造方法和操作方法，以在衬底的上部上形成具有一定宽度和高度的多个相同的硅销。 局部位线（LBL1）经由第一选择晶体管（ST11）连接到位线（BL1，BL2，BLn）。 存储单元（M11〜Mm1）与本地位线和本地源极线并联连接。 本地源极线（LSL1）通常连接到各个存储单元的源极，并且公共源极线（CSL）经由第二选择晶体管连接到本地源极线（ST21）。 漏极选择线（DSL）和源选择线（SSL）电连接到第一选择晶体管的栅极和第二选择晶体管的栅极。 多个字线（WL1至WLm）连接到每个存储单元的栅极。 局部位线和局部源极线具有与硅引脚垂直间隔开的第一掺杂层和第二掺杂层。

公开(公告)号：KR100804738B1

公开(公告)日：2008-02-19

申请号：KR1020070004973

申请日：2007-01-16

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 고형수 ,  박병국 ,  홍승범 ,  박철민 ,  최우영 ,  김종필 ,  송재영 ,  김상완

IPC: H01L21/66 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78 ,  G01R1/067

Abstract: A semiconductor probe using an impact-ionization semiconductor device is provided to remarkably improve the limit of sensitivity of a resistive probe and easily adjust the quantity of charges capable of being detected by a probe by developing a new probe structure for easily adjusting the band energy of a source. One tilted surface of a probe is formed by an anisotropic etch process using a first etch mask pattern formed on a silicon substrate. After impurities are doped into the exposed substrate to form a first semiconductor electrode region(16), the first etch mask pattern is removed. A second etch mask pattern opposite to the direction of the first etch mask pattern is formed on the silicon substrate. Space layers are formed on the sidewalls of the second etch mask pattern. After the exposed silicon substrate is anisotropically etched to form an opposite tilted surface of the probe, the second etch mask pattern is removed. Impurities are doped into the exposed substrate to form a second semiconductor electrode region(18), and the second etch mask pattern is removed. A silicon oxide layer pattern is formed on the resultant structure by a known method. Space layers are formed on both sidewalls of the silicon oxide layer pattern. By using the space layer, a predetermined depth of the silicon substrate is etched by a photolithography process, and the space layer is removed. The first semiconductor electrode region can be a source terminal, and the second semiconductor electrode region can be a drain terminal.

Abstract translation: 提供使用冲击电离半导体器件的半导体探针，以显着提高电阻式探头的灵敏度极限，并且通过开发新的探针结构容易地调节能够由探针检测的电荷量，从而容易地调节带电能 来源。 通过使用形成在硅衬底上的第一蚀刻掩模图案的各向异性蚀刻工艺形成探针的一个倾斜表面。 在将杂质掺杂到暴露的衬底中以形成第一半导体电极区域（16）之后，去除第一蚀刻掩模图案。 在硅衬底上形成与第一蚀刻掩模图案的方向相反的第二蚀刻掩模图案。 空间层形成在第二蚀刻掩模图案的侧壁上。 在暴露的硅衬底被各向异性蚀刻以形成探针的相对的倾斜表面之后，去除第二蚀刻掩模图案。 将杂质掺杂到暴露的衬底中以形成第二半导体电极区域（18），并且去除第二蚀刻掩模图案。 通过已知的方法在所得结构上形成氧化硅层图案。 空间层形成在氧化硅层图案的两个侧壁上。 通过使用空间层，通过光刻工艺蚀刻硅衬底的预定深度，并且去除空间层。 第一半导体电极区域可以是源极端子，第二半导体电极区域可以是漏极端子。

公开(公告)号：KR1020040085663A

公开(公告)日：2004-10-08

申请号：KR1020030020444

申请日：2003-04-01

Applicant: 삼성전자주식회사

Inventor： 이용규 ,  한정욱 ,  강성택 ,  이종덕 ,  박병국

IPC: H01L27/115

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

Abstract: PURPOSE: A method for fabricating a twin-ONO type SONOS memory device using a reverse self-aligning process is provided to control distribution of charges in an ONO dielectric layer by improving a SONOS memory fabrication method. CONSTITUTION: An ONO dielectric layer(500) is formed on a substrate. A buffer layer having a trench(601) is formed on the ONO dielectric layer. The ONO dielectric layer is partially exposed by the trench. The first conductive spacer(700) is formed on an inner wall of the trench. The ONO dielectric layer is divided into two parts by removing selectively the exposed part of the ONO dielectric layer. A gate dielectric layer(800) is formed on the substrate. The second conductive layer(900) is formed on the gate dielectric layer in order to fill up a gap between both sidewalls of the trench. The buffer layer is removed by using the first conductive spacer as an etch mask. The ONO dielectric layer is patterned by removing selectively the exposed part of the ONO dielectric layer.

Abstract translation: 目的：提供一种使用反向自对准工艺制造双ONO型SONOS存储器件的方法，以通过改进SONOS存储器制造方法来控制ONO电介质层中的电荷分布。 构成：在基板上形成ONO电介质层（500）。 在ONO电介质层上形成具有沟槽（601）的缓冲层。 ONO电介质层由沟槽部分露出。 第一导电间隔物（700）形成在沟槽的内壁上。 通过选择性地去除ONO介电层的暴露部分，将ONO介电层分成两部分。 在基板上形成栅介质层（800）。 为了填充沟槽的两个侧壁之间的间隙，在栅极介电层上形成第二导电层（900）。 通过使用第一导电间隔物作为蚀刻掩模去除缓冲层。 通过选择性地去除ONO电介质层的暴露部分来对ONO电介质层进行构图。

公开(公告)号：KR101658037B1

公开(公告)日：2016-09-21

申请号：KR1020100111121

申请日：2010-11-09

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 권대웅 ,  박병국 ,  김창정 ,  박재철

IPC: G09G3/30

CPC classification number: G09G3/3233 ,  G09G2300/0842 ,  G09G2310/0251

Abstract: 능동형디스플레이구동방법이개시된다. 개시된능동형디스플레이장치의구동방법은, 각화소를충전하기이전에상기화소에연결된스위칭트랜지스터에음의바이어스전압을인가하여상기스위칭트랜지스터의문턱전압을회복시키는단계를포함한다. 상기음의바이어스전압은상기스위칭트랜지스터의드레인전극에인가된다.

公开(公告)号：KR101652826B1

公开(公告)日：2016-08-31

申请号：KR1020100001878

申请日：2010-01-08

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 오정훈 ,  유경창 ,  박병국 ,  오경석 ,  백인규

IPC: G11C16/00 ,  G11C16/30 ,  G11C11/21

CPC classification number: G11C13/0002 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/102 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: 본발명은저항성메모리재료막을이용한반도체소자및 그구동방법에관한것이다. 본발명의일 실시예에따른반도체소자는, 기판상에적어도하나의메모리셀들을포함하는반도체소자이며, 상기적어도하나의메모리셀들은, 인가되는전압에따라각각저저항상태또는고저항상태로가역적으로스위칭되며, 서로직렬연결된단극가변저항및 양극가변저항을포함한다.

公开(公告)号：KR1020140046258A

公开(公告)日：2014-04-18

申请号：KR1020120112510

申请日：2012-10-10

Applicant: 삼성전자주식회사 ,  서울대학교산학협력단

Inventor： 선민철 ,  박병국

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823412 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/02647 ,  H01L21/3065 ,  H01L27/088 ,  H01L27/1222 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/772 ,  H01L29/7843 ,  H01L29/78651 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: Provided is a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate having first and second areas separated from each other; a structure formed on the substrate and formed by alternately laminating at least one sacrificial layer and at least one active layer; a first gate-all-around device formed in a first area and including a first nanowire; and a second gate-all-around device formed in a second area and including a second nanowire. The first nanowire is formed at the same level as that of a first active layer among the at least one active layer, and the second nanowire is formed at the same level as that of a second active layer among the at least one active layer. The first active layer is different from the second active layer.

Abstract translation: 提供一种半导体器件及其制造方法。 半导体器件包括具有彼此分离的第一和第二区域的衬底; 通过交替地层叠至少一个牺牲层和至少一个有源层而形成在所述基板上的结构; 形成在第一区域中并且包括第一纳米线的第一栅极全能器件; 以及形成在第二区域中并且包括第二纳米线的第二栅极全能器件。 第一纳米线形成在与至少一个有源层中的第一有源层相同的电平上，并且第二纳米线形成在与至少一个有源层中的第二有源层相同的电平上。 第一活性层与第二活性层不同。

公开(公告)号：KR1020130083315A

公开(公告)日：2013-07-22

申请号：KR1020120004031

申请日：2012-01-12

Applicant: 삼성전자주식회사

Inventor： 김영식 ,  홍성복 ,  이형진 ,  이정철 ,  허종인 ,  박병국 ,  신봉철

IPC: H01L21/50

Abstract: PURPOSE: Semiconductor equipment is provided to increase an operation speed by including a transfer device which bidirectionally transfers a substrate. CONSTITUTION: A transfer device is located on a die attaching device and a wire bonding device. The transfer device includes a rail (210), a movable structure mounted on the rail, and a support structure mounted on the movable structure. The movable structure includes a slider (221) which moves on the rail and a driving motor (222) attached to one side of the slider. The support structure mounts a substrate (400). The support structure includes a first mounting unit (231), a second mounting unit (232), and a fixing unit (233).

Abstract translation: 目的：提供半导体设备以通过包括双向传送衬底的传送装置来提高操作速度。 构成：转移装置位于模具附着装置和引线接合装置上。 传送装置包括轨道（210），安装在轨道上的可移动结构以及安装在可移动结构上的支撑结构。 可移动结构包括在轨道上移动的滑块（221）和附接到滑块的一侧的驱动马达（222）。 支撑结构安装基板（400）。 支撑结构包括第一安装单元（231），第二安装单元（232）和固定单元（233）。