公开(公告)号：KR1020050029423A

公开(公告)日：2005-03-28

申请号：KR1020030065679

申请日：2003-09-22

Applicant: 삼성전자주식회사

Inventor： 이용선 ,  유재민 ,  이돈우 ,  조정훈 ,  권철순 ,  문정호 ,  윤인구 ,  박재현

IPC: H01L27/115

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A method of fabricating a flash memory cell having a split gate structure is provided to form a gate interlayer dielectric pattern having an uniform thickness by a CVD(Chemical Vapor Deposition) process and a planarization process. A first gate insulating layer(21), a floating gate layer, and a sacrificial layer are formed on a semiconductor substrate(20). A sacrificial layer pattern having an opening for exposing a part of the floating gate layer is formed by patterning the sacrificial layer. A gate interlayer dielectric pattern is formed within the opening. The sacrificial layer pattern is removed therefrom. A floating gate is formed under the gate interlayer dielectric pattern by etching the floating gate layer. A second gate insulating layer(25) is formed on the semiconductor substrate. A control gate(26) is formed on the second gate insulating layer.

Abstract translation: 提供一种制造具有分裂栅极结构的闪存单元的方法，以通过CVD（化学气相沉积）工艺和平坦化工艺形成具有均匀厚度的栅极层间电介质图案。 在半导体衬底（20）上形成第一栅绝缘层（21），浮栅层和牺牲层。 通过图案化牺牲层来形成具有用于暴露浮栅的一部分的开口的牺牲层图案。 在开口内形成栅极层间电介质图案。 从中除去牺牲层图案。 通过蚀刻浮栅，在栅极层间介质图案下方形成浮栅。 在半导体衬底上形成第二栅极绝缘层（25）。 控制栅极（26）形成在第二栅极绝缘层上。

公开(公告)号：KR1020040105005A

公开(公告)日：2004-12-14

申请号：KR1020030035603

申请日：2003-06-03

Applicant: 삼성전자주식회사

Inventor： 박상욱 ,  유재민 ,  권철순 ,  김진우 ,  박재현 ,  김용희 ,  이돈우 ,  김대근 ,  김주찬 ,  김국민 ,  류의열

IPC: H01L21/027

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor device and a measuring method of the semiconductor device using the same is provided to reduce a dishing defect, thereby enhancing a measurement reliability by improving a measuring pattern. CONSTITUTION: A semiconductor device has a chip region for integrated circuit and a scribe region surrounding the chip region. A measuring pattern (42) is formed in the scribe region to have a trench shape in the substrate. A plurality of dummy patterns is formed in the measuring pattern, thereby reducing the surface area of the measuring pattern. In spite of the succeeding process of CMP(Chemical and Mechanical Polishing), a dishing defect due to large surface area is capable of being reduced.

Abstract translation: 目的：提供半导体器件和使用其的半导体器件的测量方法以减少凹陷缺陷，从而通过改进测量图案来提高测量可靠性。 构成：半导体器件具有用于集成电路的芯片区域和围绕芯片区域的划线区域。 在划片区域中形成测量图案（42），以在衬底中具有沟槽形状。 在测量图形中形成多个虚设图案，从而减小测量图案的表面积。 尽管CMP（化学和机械抛光）的成功进程，由于表面积大而导致的凹陷缺陷能够减少。

公开(公告)号：KR1020040023857A

公开(公告)日：2004-03-20

申请号：KR1020020055292

申请日：2002-09-12

Applicant: 삼성전자주식회사

Inventor： 조인수 ,  유재민 ,  전병구 ,  유준열 ,  이창엽

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: PURPOSE: A method for fabricating a non-volatile memory(NVM) device is provided to minimize thermal budget generated when a lower sacrificial layer is thickly formed, by forming an upper sacrificial layer made of a material like a silicon oxide layer having etch selectivity on the lower sacrificial layer. CONSTITUTION: A lower conductive layer is formed on a semiconductor substrate(100). A lower sacrificial layer pattern(135) having an opening exposing the lower conductive layer and an upper sacrificial layer pattern(145) are formed on the substrate including the lower conductive layer. A mask spacer(170) is formed on the sidewall of the upper and lower sacrificial layer patterns. The exposed lower conductive layer is etched by using the mask spacer and the upper sacrificial layer pattern as an etch mask so as to form a lower conductive layer pattern exposing the substrate. A plug conductive layer is formed to cover the front surface of the substrate including the lower conductive layer pattern. The plug conductive layer is planarization-etched until the lower sacrificial layer pattern is exposed, so that a source plug which fills a gap region between the mask spacers and is connected to the substrate is formed.

Abstract translation: 目的：提供一种用于制造非易失性存储器（NVM）器件的方法，用于通过形成由诸如具有蚀刻选择性的氧化硅层的材料制成的上牺牲层来最小化当下牺牲层厚度形成时产生的热预算 下牺牲层。 构成：在半导体衬底（100）上形成下导电层。 在包括下导电层的基板上形成具有暴露下导电层的开口的下牺牲层图案（135）和上牺牲层图案（145）。 掩模间隔物（170）形成在上和下牺牲层图案的侧壁上。 通过使用掩模间隔物和上牺牲层图案作为蚀刻掩模来蚀刻暴露的下导电层，以形成露出衬底的下导电层图案。 形成插塞导电层以覆盖包括下导电层图案的基板的前表面。 插塞导电层被平坦化蚀刻，直到下部牺牲层图案露出，从而形成填充掩模间隔物之间​​的间隙区域并与衬底连接的源极插塞。