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公开(公告)号：KR101852989B1
公开(公告)日：2018-04-30
申请号：KR1020110040140
申请日：2011-04-28
Applicant: 삼성전자주식회사
CPC classification number: G02F1/133 , H01L23/3121 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/01322 , H01L2924/3025 , H01L2924/00012 , H01L2924/00
Abstract: 본발명은정전기나기타전기적충격으로부터반도체칩을보호할수 있게하는반도체패키지장치에관한것으로서, 반도체칩; 상기반도체칩을지지하는기판; 상기기판에형성되고, 상기반도체칩과전기적으로연결되는적어도하나의단자; 임계전압이인가되면절연성에서도전성으로변하는감전압성물질(voltage sensitive material)을포함하여이루어지고, 상기반도체칩을둘러싸서보호하는제 1 봉지재; 상기제 1 봉지재에인가된정전기를외부로유도하는정전기유도단자; 및상기제 1 봉지재와상기정전기유도단자사이에설치되고, 상기정전기를상기정전기유도단자로유도하는정전기차단부재;를포함한다.
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公开(公告)号：KR1020170085932A
公开(公告)日：2017-07-25
申请号：KR1020160059712
申请日：2016-05-16
Applicant: 삼성전자주식회사
IPC: H01L23/00 , H01L23/373 , H01L23/498 , H01L23/31 , H01L25/10
CPC classification number: H01L24/19 , H01L21/568 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73267 , H01L2224/94 , H01L2224/96 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/15311 , H01L2924/1815 , H01L2924/18162 , H01L2924/3025 , H01L2924/3511 , H01L2924/00014 , H01L2224/83
Abstract: 본발명은반도체패키지를제공한다. 반도체패키지는재배선기판; 상기재배선기판상에배치되고, 그내부를관통하는홀을갖는연결기판; 상기재배선기판상에제공되며, 상기연결기판의상기홀 내에제공된반도체칩; 상기반도체칩의상면상에배치된금속층; 및상기반도체칩및 상기연결기판사이의갭에제공되는몰딩막을포함할수 있다. 상기연결기판은베이스층들및 상기베이스층들내의도전부를포함할수 있다. 상기연결기판의상면은상기금속층의상면보다낮은레벨에배치될수 있다.
Abstract translation: 本发明提供了一种半导体封装。 半导体封装包括重新布线板; 配置在再布线基板上且贯通内部的孔的连接基板; 设置在所述重写板上并设置在所述连接板的所述孔中的半导体芯片; 设置在半导体芯片上的金属层; 并且设置在半导体芯片和连接基板之间的间隙中的成型膜。 连接基板可以包括基层和基层中的导电部分。 连接基板的上表面可以设置在比金属层的上表面低的水平面上。
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公开(公告)号：KR1020160146035A
公开(公告)日：2016-12-21
申请号：KR1020150082569
申请日：2015-06-11
Applicant: 삼성전자주식회사
IPC: H01L25/065 , H01L23/00 , H01L23/28
CPC classification number: H01L23/562 , H01L21/561 , H01L21/565 , H01L23/3114
Abstract: 본발명의기술적사상에의한웨이퍼레벨패키지는, 기판, 기판상에실장된복수의반도체칩들, 그리고기판및 복수의반도체칩들과접촉하면서기판상에형성된몰딩부재를포함하고, 몰딩부재는열 팽창계수가서로다른적어도둘 이상의부분으로이루어진것을특징으로한다.
Abstract translation: 水位封装包括基板，安装在基板上的多个半导体芯片，以及与基板和多个半导体芯片接触并形成在基板上的模制部件。 模制构件包括两个或更多个具有彼此不同的热膨胀系数（CTE）的模制构件。
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Patent Agency Ranking
公开(公告)号：KR101680115B1
公开(公告)日：2016-11-29
申请号：KR1020100017747
申请日：2010-02-26
Applicant: 삼성전자주식회사
IPC: H01L23/00 , H01L23/498
CPC classification number: H01L24/50 , H01L23/4985 , H01L24/06 , H01L2224/0401 , H01L2224/0405 , H01L2224/05553 , H01L2224/06155 , H01L2224/14155 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
Abstract: 라우팅공간이확보된탭 패키지용반도체칩이제공된다. 탭패키지용반도체칩은센터영역과엣지영역을포함하는접속면, 접속면의엣지영역에배치되어입력신호를제공받는다수의입력패드, 접속면의엣지영역에배치되어제1 출력신호를제공하는다수의제1 출력패드, 및접속면의센터영역에배치되어제2 출력신호를제공하는다수의제2 출력패드를포함한다.
Abstract translation: 公开了一种用于带式自动接合（TAB）封装的半导体芯片。 半导体芯片包括连接表面，其包括连接到芯片的内部电路的一组输入焊盘，并且用于将外部信号传送到内部电路，该组输入焊盘包括芯片上的所有输入焊盘。 连接表面包括连接到芯片的内部电路的一组输出焊盘，并将内部芯片信号传送到芯片外部，该组输出焊盘包括芯片上的所有输出焊盘。
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公开(公告)号：KR1020160017796A
公开(公告)日：2016-02-17
申请号：KR1020140100634
申请日：2014-08-05
Applicant: 삼성전자주식회사
CPC classification number: H05K1/189 , H01L21/561 , H01L23/13 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/562 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/165 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2224/97 , H01L2225/06517 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/15153 , H01L2924/15159 , H01L2924/15311 , H01L2924/15331 , H01L2924/19106 , H01L2924/3511 , H05K1/028 , H05K1/181 , H05K3/4697 , H05K2201/09845 , H05K2201/10515 , H05K2201/10522 , H05K2201/1053 , H05K2201/10734 , H05K2201/10977 , H01L2224/83 , H01L2224/81
Abstract: 본발명은반도체패키지및 반도체모듈을제공한다. 본발명에따른반도체모듈은모듈기판; 및상기모듈기판상에실장되는반도체패키지를포함할수 있다. 반도체패키지의기판은편평한상면및 제1 영역및 상기제1 영역보다낮은레벨을갖는제2 영역을포함하는하면을가질수 있다. 상기제2 영역상의상기연결부의하부면은상기제1 영역상의연결부의하부면보다낮은레벨을가질수 있다. 연결부는상기기판의하면상에서상기모듈기판과전기적으로연결될수 있다.
Abstract translation: 本发明提供一种半导体封装和半导体模块。 根据本发明，半导体模块包括：模块基板; 以及安装在模块基板上的半导体封装。 半导体封装的衬底具有顶表面和底表面，其中顶表面是平坦的，并且底表面包括第一区域和具有比第一区域低的水平的第二区域。 第二区域上的连接部分的下表面具有比第一区域上的连接部分的下表面更低的水平。 连接部分电连接到基板的底表面上的模块基板。
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公开(公告)号：KR1020130105163A
公开(公告)日：2013-09-25
申请号：KR1020120027359
申请日：2012-03-16
Applicant: 삼성전자주식회사
IPC: H01L23/60
CPC classification number: H01L23/5256 , H01L23/4985 , H01L23/60 , H01L2924/0002 , H02H9/041 , H01L2924/00
Abstract: PURPOSE: A semiconductor package and a display device including the same are provided to distribute static electricity to a ground layer or to output the static electricity to the outside by including a via contact which electrically connects a wiring pattern to the ground layer in a non-mounting area. CONSTITUTION: A base film (20) has a first surface and a second surface which faces the first surface. The base film is composed of a first area and a second area. A wiring pattern is formed on the first surface of the base film in the second area. An insulation layer (26) is arranged on the wiring pattern of the second area. A ground layer (28) is arranged on the second surface of the base film. A semiconductor chip (10) is mounted on the first surface of the base film in the first area.
Abstract translation: 目的：提供一种半导体封装和包括该半导体封装的显示装置，用于将静电分配到接地层，或通过包括以非导电方式将布线图案与接地层电连接的通孔接点将静电输出到外部， 安装区域。 构成：基膜（20）具有面向第一表面的第一表面和第二表面。 基膜由第一区域和第二区域构成。 在第二区域中的基膜的第一表面上形成布线图案。 绝缘层（26）布置在第二区域的布线图案上。 接地层（28）布置在基膜的第二表面上。 半导体芯片（10）安装在第一区域的基膜的第一表面上。
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公开(公告)号：KR1020130102405A
公开(公告)日：2013-09-17
申请号：KR1020120023607
申请日：2012-03-07
Applicant: 삼성전자주식회사
CPC classification number: H01L23/36 , G01N29/0681 , H01L21/56 , H01L22/12 , H01L23/3128 , H01L23/3185 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/14131 , H01L2224/14135 , H01L2224/16225 , H01L2224/16227 , H01L2224/29011 , H01L2224/32221 , H01L2224/73253 , H01L2224/81815 , H01L2224/8385 , H01L2224/92225 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/00014 , H01L2924/00
Abstract: PURPOSE: A flip chip package and a method for manufacturing the same are provided to prevent the scattering of ultrasound by forming an opening part for exposing the upper part of a semiconductor chip. CONSTITUTION: A semiconductor chip is arranged on the upper part of a package substrate. The semiconductor chip and the package substrate are electrically connected by conductive bumps (130). A molding material (150) covers the semiconductor chip. A heat sink (140) includes an opening part. The opening part exposes the upper surface of the semiconductor chip.
Abstract translation: 目的：提供一种倒装芯片封装及其制造方法，以通过形成用于暴露半导体芯片的上部的开口部来防止超声波的散射。 构成：半导体芯片布置在封装衬底的上部。 半导体芯片和封装基板通过导电凸块（130）电连接。 成型材料（150）覆盖半导体芯片。 散热器（140）包括开口部。 开口部露出半导体芯片的上表面。
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公开(公告)号：KR1020080043068A
公开(公告)日：2008-05-16
申请号：KR1020060111622
申请日：2006-11-13
Applicant: 삼성전자주식회사
CPC classification number: H01L2224/16 , H01L2924/01079
Abstract: A semiconductor device having a chip on film structure and a method of manufacturing the same are provided to prevent a bump from being twisted due to thermal stress after adhesion between a bond finger and the bump. A semiconductor device having a chip on film structure includes a semiconductor chip(310), a bump(340), a resin layer(330), a circuit board(370), and a bond finger(360). The semiconductor chip has pads. The bump is attached to the pad. The resin layer covers the semiconductor chip around the bump and protrudes from the bump. The circuit board overlaps with the semiconductor chip. The bond finger is disposed on the circuit board and comes in contact with the bump. The bond finger protrudes from the circuit board to the bump. The circuit board is a flexible circuit printed board. The resin layer is made of photoresist material.
Abstract translation: 提供一种具有薄膜结构芯片的半导体器件及其制造方法，以防止在粘合指状物和凸点之间的粘合之后由于热应力而使凸起扭曲。 具有薄膜结构芯片的半导体器件包括半导体芯片（310），凸块（340），树脂层（330），电路板（370）和粘合指（360）。 半导体芯片具有焊盘。 凸块连接到垫上。 树脂层覆盖凸起周围的半导体芯片并从凸块突出。 电路板与半导体芯片重叠。 接合指状物设置在电路板上并与凸块接触。 接合指状物从电路板突出到凸块。 电路板是柔性电路印刷电路板。 树脂层由光致抗蚀剂材料制成。
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