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    MIM CAPACITOR AND METHOD OF FABRICATING SAME
    33.
    发明申请
    MIM CAPACITOR AND METHOD OF FABRICATING SAME 审中-公开
    MIM电容器及其制造方法

    公开(公告)号：WO2006113158A3

    公开(公告)日：2007-03-01

    申请号：PCT/US2006012904

    申请日：2006-04-07

    Applicant: IBM ,  YANG CHIH-CHANO ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C

    Inventor： YANG CHIH-CHANO ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C

    IPC: H01L21/8242 ,  H01L21/20

    CPC classification number: H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIM capacitor includes a dielectric layer (140) having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer (140); a first plate of a MIM capacitor comprising a conformal conductive liner (175) formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer (190) formed over a top surface of the conformal conductive liner; and a second plate (195) of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.

    Abstract translation: 一种镶嵌MIM电容器和一种制造MIM电容器的方法。 MIM电容器包括具有顶表面和底表面的电介质层（140） 所述电介质层中的沟槽，所述沟槽从所述介电层（140）的顶表面延伸到所述底表面; MIM电容器的第一板包括形成在所有侧壁上并沿着沟槽的底部延伸的共形导电衬垫（175），沟槽的底部与电介质层的底表面共面; 绝缘层（190），形成在所述共形导电衬垫的顶表面上; 和MIM电容器的第二板（195），其包括与所述绝缘层直接物理接触的芯导体，所述沟槽中的所述芯导体填充空间未被所述共形导电衬垫和所述绝缘层填充。 该方法包括与镶嵌互连线同时形成MIM电容器的一部分。

    DIAMOND AS A POLISH-STOP LAYER FOR CHEMICAL-MECHANICAL PLANARIZATION IN A DAMASCENE PROCESS FLOW
    34.
    发明申请
    DIAMOND AS A POLISH-STOP LAYER FOR CHEMICAL-MECHANICAL PLANARIZATION IN A DAMASCENE PROCESS FLOW 审中-公开
    金刚石作为化学机械平面化在抛物线工艺流程中的抛物面层

    公开(公告)号：WO0195382A3

    公开(公告)日：2002-08-29

    申请号：PCT/US0118539

    申请日：2001-06-07

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS ,  STEPHENS JEREMY K ,  WISE MICHAEL

    IPC: H01L21/76 ,  H01L21/285 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768

    CPC classification number: H01L21/31053 ,  H01L21/28525 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684

    Abstract: A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A protective layer is then deposited over the diamond or diamond-like carbon polish-stop layer, wherein such protective layer may act as an additional polish-stop layer. Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features, wherein such protective layer protects the diamond or diamond-like carbon polish-stop layer during the patterning process. After deposition of a conductive metal layer, the dielectric substrate is polished to remove excess conductive material, as well as topography. In the polishing process, the diamond or diamond-like carbon polish-stop layer and any remaining protective layer are used as polish-stop layers. The diamond or diamond-like carbon polish-stop layer allows for an improved planar surface, thereby resulting in an sufficient decrease in topography at the surface of the inter-level dielectric.

    Abstract translation: 使用金刚石或类金刚石碳层作为抛光停止件的方法，其使用镶嵌工艺流程将金属层图案化成层间电介质基板。 在图案化金属层之前，将金刚石或类金刚石碳层沉积在基板的表面上。 然后将保护层沉积在金刚石或类金刚石碳抛光层上，其中这种保护层可以用作另外的抛光停止层。 一起使用金刚石或类金刚石碳抛光层和保护层作为用于图案化将成为金属特征的沟槽的硬掩模，其中这种保护层保护金刚石或类金刚石碳抛光 在图案化过程中。 在沉积导电金属层之后，电介质基底被抛光以除去过量的导电材料以及形貌。 在抛光过程中，将金刚石或类金刚石碳抛光层和任何剩余的保护层用作抛光 - 停止层。 金刚石或类金刚石碳抛光层允许改进的平面表面，从而导致层间电介质表面的形貌的充分降低。

    INTEGRATED CIRCUIT SYSTEM WITH CARBON ENHANCEMENT
    35.
    发明专利
    INTEGRATED CIRCUIT SYSTEM WITH CARBON ENHANCEMENT 未知

    公开(公告)号：SG165342A1

    公开(公告)日：2010-10-28

    申请号：SG2010064129

    申请日：2008-02-20

    Applicant: GLOBALFOUNDRIES SG PTE LTD ,  IBM

    Inventor： WUPING LIU ,  WIDODO JOHNNY ,  PETRARCA KEVIN S ,  CLEVENGER LAWRENCE A ,  WAI-KIN LI

    Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a carbon implant region around the via opening, a trench opening, or a combination thereof, for protecting the low-K dielectric layer. FIG 1

    INTERCONNECTS WITH IMPROVED TDDB
    36.
    发明专利
    INTERCONNECTS WITH IMPROVED TDDB 未知

    公开(公告)号：SG159483A1

    公开(公告)日：2010-03-30

    申请号：SG2009056896

    申请日：2009-08-26

    Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

    Inventor： HUI LI JING ,  PING LIU WU ,  CLEVENGER LAWRENCE A

    Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

    INTEGRATED CIRCUIT SYSTEM WITH CARBON ENHANCEMENT
    38.
    发明专利
    INTEGRATED CIRCUIT SYSTEM WITH CARBON ENHANCEMENT 未知

    公开(公告)号：SG146528A1

    公开(公告)日：2008-10-30

    申请号：SG2008014136

    申请日：2008-02-20

    Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

    Inventor： WUPING LIU ,  WIDODO JOHNNY ,  PETRARCA KEVIN S ,  CLEVENGER LAWRENCE A ,  WAI-KIN LI

    Abstract: INTEGRATED CIRCUIT SYSTEM WITH CARBON ENHANCEMENT An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a carbon implant region around the via opening, a trench opening, or a combination thereof, for protecting the low-K dielectric layer.

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