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    ACTIVE FET BODY DEVICE AND MANUFACTURE THEREFOR
    31.
    发明专利
    ACTIVE FET BODY DEVICE AND MANUFACTURE THEREFOR 失效

    公开(公告)号：JP2000058861A

    公开(公告)日：2000-02-25

    申请号：JP22482799

    申请日：1999-08-09

    Applicant: IBM

    Inventor： ASSADERAGHI FARIBORZ ,  BERTIN CLAUDE L ,  GAMBINO JEFFREY P ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

    IPC: H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/84 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To obtain an active FET body device capable of balancing high-speed electric charges, decreasing off-current, and increasing on-current. SOLUTION: This embodiment comprises a silicon substrate 2, a silicon dioxide layer 3, a monocrystal silicon layer 4, a silicon dioxide layer 5, a spacer 13 of N+ doped polysilicon, a conformal layer 15 of a conductive diffusion preventing substance, a metal silicide layer 16, a CVD silicon dioxide layer 17, an insulator spacer 18, a silicon oxide layer 19, and a polysilicon 21. In an off-state, a gate contact with a body holds the body at a low word line level. In this state, a threshold takes a larger value. In addition to a voltage added to the N+ part 13 of a gate conductor, a potential from the body to a source rises. As a result, if the device is turned on, Vt lowers. By the effects of a dynamic Vt fall accompanied by a low off-current, this embodiment is suitable for a device using a very low voltage.

    SEMICONDUCTOR STRUCTURE CONTAINING CONDUCTIVE FUSE AND ITS MANUFACTURE
    32.
    发明专利
    SEMICONDUCTOR STRUCTURE CONTAINING CONDUCTIVE FUSE AND ITS MANUFACTURE 失效

    公开(公告)号：JP2000058655A

    公开(公告)日：2000-02-25

    申请号：JP17440199

    申请日：1999-06-21

    Applicant: IBM

    Inventor： ARNDT KENNETH C ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  NARAYAN CHANDRASEKHAR ,  SCHNABEL RAINER F ,  SCHUTZ RONALD J ,  TOEBBEN DIRK

    IPC: H01L21/82 ,  H01L21/768 ,  H01L23/525

    Abstract: PROBLEM TO BE SOLVED: To improve the control of thickness of an insulator layer on a fuse structure, by a method wherein a dielectric structure is positioned on a conduction level, and electric connection is performed at a selected position of the conduction level through the dielectric structure. SOLUTION: On a semiconductor substrate 10 an electric conduction level 1 is formed by using conductive material selected out of aluminum, copper, aluminum copper alloy, and doped polysilicon having metal type conductivity. A dielectric etching stop material layer 2 is stuck on the upper surface of the electric conduction level 1. Electric connection is performed to a selected position of the electric conduction level 1 through the dielectric etching stop material layer 2, and a conductive fuse 21 is constituted. As a result control of the thickness of an insulator layer on the fuse structure containing a self-aligned isolation cap can be improved.

    TRENCH CAPACITOR STRUCTURE AND MANUFACTURE THEREOF
    33.
    发明专利
    TRENCH CAPACITOR STRUCTURE AND MANUFACTURE THEREOF 失效

    公开(公告)号：JP2000022101A

    公开(公告)日：2000-01-21

    申请号：JP15133899

    申请日：1999-05-31

    Applicant: IBM ,  SIEMENS AG

    Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  KAARU JIEI RADENSU

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: PROBLEM TO BE SOLVED: To reduce remarkably the distributed series resistance of trench electrodes, by manufacturing trench capacitors using a method of forming heat- resistant metallic salicide materials on the trench regions having low trench capacitors. SOLUTION: A narrow upper region 16a and a wide lower region 16b are filled with ploysilicon layers 26 and the polysilicon layers 26 are planarized. Next, the polysilicon layers 26 are recessed, then conformal heat-resistant metallic layers 30 are adhered. After that, the salicide is formed at the interface between the heat-resistant metal in the region 16b and the polysilicon by annealing. As a result, a heat-resistant metallic salicide layer 32 is formed in the wide lower trench region 16b. It is preferable that the heat-resistant metallic salicide layer is not formed in the narrow upper trench region 16b. Next, the heat-resistant metallic layer 30 remained in the upper layer 16a is removed. Then, the additional polysilicon is filled in the trench. After that, the capacitor structure is planarized.

    FORMATION OF ELECTRICAL CONNECTION TO STUD
    35.
    发明专利
    FORMATION OF ELECTRICAL CONNECTION TO STUD 失效

    公开(公告)号：JPH11251429A

    公开(公告)日：1999-09-17

    申请号：JP3199

    申请日：1999-01-04

    Applicant: IBM

    Inventor： BRONNER GARY B ,  GAMBINO JEFFREY P

    IPC: H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To provide an improved damascene process for forming an interconnect to a conductive stud. SOLUTION: An electrical connection to a stud is made by filling a conductive stud material in a contact hole formed in a dielectric material layer 7, patterning the conductive stud material, removing a shallow part of the dielectric material layer surrounding the conductive stud material, depositing a second dielectric material layer 9, forming a trench in the second dielectric material layer in an upper region of the conductive stud, and patterning a conductive material in the trench.

    FORMATION OF INTEGRATED CIRCUIT
    36.
    发明专利
    FORMATION OF INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11163302A

    公开(公告)日：1999-06-18

    申请号：JP27902398

    申请日：1998-09-30

    Applicant: SIEMENS AG ,  IBM

    Inventor： GAMBINO JEFFREY P ,  ALSMEIER JOHANN ,  BRONNER GARY

    IPC: H01L27/108 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To respond effectively and readily to contradictory requests chip regions by separating a first region from a second region by means of an insulation region. SOLUTION: A substrate 101 comprises at least a part of first and second regions 110, 130. An insulation region 150 is a shallow trench insulator(STI) comprising a dielectric material, such as oxide. The second region is an array region of a DRAMIC. An insulation region such as an STI is provided for separating a trench capacitor, for example. A region is provided by a well of dopant for a device to be formed next. Various layers forming a gate stack of a device are formed on the surface of a substrate. The process includes the formation of an oxide layer 160 through thermal oxidation, for example. The oxide layer 160 is used as a gate oxide. The gate layer 161 is deposited on a gate oxide. The gate layer 161 is a composite layer such as polycide.

    METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION
    40.
    发明申请
    METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION 审中-公开
    金属绝缘体 - 金属电容器和制造方法

    公开(公告)号：WO2005034201A3

    公开(公告)日：2007-12-06

    申请号：PCT/US2004032405

    申请日：2004-09-30

    Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

    Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

    IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interievel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interievel dielectric layer, atop surface of the bottom electrode co-planer with a top surface of the interievel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

    Abstract translation: 一种MIM电容器的方法和结构，所述结构包括：电子器件，包括：形成在半导体衬底上的电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的顶表面具有所述电介质层的顶表面; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

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