中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

50 records (took 0.035 seconds)

    31.
    发明专利
    未知

    公开(公告)号：DE3850901D1

    公开(公告)日：1994-09-08

    申请号：DE3850901

    申请日：1988-03-29

    Applicant: IBM

    Inventor： BLOKKUM DAG REIDAR ,  JOHNS CHARLES RAY ,  MOROZINK LEE JACK ,  PETERSON DAVID LAWRENCE

    IPC: G06F12/06

    Abstract: A system and method for contiguously addressing a memory system comprising a plurality of memory banks, each of which can have different capacity modules, or no module, plugged therein, comprises a matrix of logic cells. Each row of the cells receives a group of segment signal lines each indicating consecutively a fixed sized memory address segment. Each column receives a group of signals representing the capacity of memory modules currently in a corresponding memory bank. Taking the cell at row 1, column 1, if memory bank 1 contains the maximum capacity, then segment signals, when they appear on any of the four segment signal lines, pass through the column to form part of the memory addresses. If, however, memory bank 1 contains memory modules having an address range corresponding to, say, one segment, only the segment 1 line passes logically through the column. Except when the bank contains no memory, a bank 1 select signal (BS1) is generated. The second column of logic cells receives the first eight segment lines. If both banks 1 and 2 contain maximum capacity modules, then all eight segment lines pass through rows 1 and 2. If, however, bank 1 contains only one segment of memory, the memory cell 34 at row 1, column 2, picks up to three of the segment lines, depending on how many segments are in bank 2, and memory cell 32 at row 2, column 2 will pick the remaining segment line 5, if there are four segments in memory bank 2. In this way, the segment lines are picked consecutively, irrespective of the mix of modules in the memory banks.

    ENHANCED HIGH PERFORMANCE PCI
    35.
    发明专利
    ENHANCED HIGH PERFORMANCE PCI 未知

    公开(公告)号：CA2236060A1

    公开(公告)日：1998-12-11

    申请号：CA2236060

    申请日：1998-04-28

    Applicant: IBM

    Inventor： NEAL DANNY MARVIN ,  THURBER STEVEN MARK ,  CLOUSER PAUL L ,  JOHNS CHARLES RAY ,  KELLEY RICHARD ALLEN

    IPC: G06F13/00 ,  G06F13/368 ,  G06F13/38

    Abstract: A peripheral component interconnect (PCI) bus is adapted for differential signal ling. Two signal lines are providing for each bus signal and information is encoded as either a polarity or a magnitude of a voltage difference between the two signal lines. En hanced PCI compliant devices include drivers and receivers capable of differential sign alling. The resulting bus architecture supports clocking data on both edges as well as sourc e synchronous clocking. The enhanced PCI bus architecture also supports data block ing, pacing, split transactions, and synchronization commands.

    METHOD AND APPARATUS FOR POWER THROTTLING A PROCESSOR IN AN INFORMATION HANDLING SYSTEM
    37.
    发明专利
    METHOD AND APPARATUS FOR POWER THROTTLING A PROCESSOR IN AN INFORMATION HANDLING SYSTEM 未知

    公开(公告)号：CA2667422A1

    公开(公告)日：2008-07-17

    申请号：CA2667422

    申请日：2007-12-19

    Applicant: IBM

    Inventor： JOHNS CHARLES RAY ,  BERRY ROBERT WALTER JR ,  KURUTS CHRISTOPHER

    IPC: G06F1/32

    Abstract: A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the proce ssor when the power that the processor consumes from thepower systemexceeds a predetermined threshold power. The power systemmay reduce the rate of inst ruction issue by a particular core or clock gate a particular core to provid e power throttling. The power system dynamically responds to variance of the actualoutput voltage that processor circuitryreceives from the power system in comparison to an expected output voltage over time and corrects for such variance.

Patent Agency Ranking