公开(公告)号：SG43875A1

公开(公告)日：1997-11-14

申请号：SG1996003608

申请日：1991-01-24

Applicant: IBM

Inventor： BARTH JOHN EDWARD JR ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

IPC: G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C11/401 ,  G06F11/20

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：HK62097A

公开(公告)日：1997-05-16

申请号：HK62097

申请日：1997-05-08

Applicant: IBM

Inventor： BARTH JOHN EDWARD JR ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

IPC: G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C11/401 ,  G06F11/20

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：DE69026743D1

公开(公告)日：1996-06-05

申请号：DE69026743

申请日：1990-02-02

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：DE69019665T2

公开(公告)日：1996-01-25

申请号：DE69019665

申请日：1990-09-07

Applicant: IBM

Inventor： DRAKE CHARLES EDWARD ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE

IPC: H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948

Abstract: A CMOS integrated circuit for driving capacitance has an input node (10) and an output node (20) and includes a first transistor (14) operatively connected to the input node (10) which is turned "on" and "off" by the input node (10) to supply an output signal to the output node (20) when turned "on". A second transistor (24) is provided, the output of which is connected to the output node (20) when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor (14) prior to the second transistor (24), and to turn on the second transistor (24) if and only if the slew rate of the output signal of the first transistor (14) is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor (14) will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor (24); however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor (14) will cause the second transistor (24) to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

公开(公告)号：DE69012395D1

公开(公告)日：1994-10-20

申请号：DE69012395

申请日：1990-03-13

Applicant: IBM

Inventor： FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  G11C7/00 ,  G11C11/409

Abstract: This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit lines (e.g. BL2, BL2 min ) are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines (e.g. BL1, BL1 min and/or BL3, BL3 min ) as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines (BL1, BL2; BL1 min , BL2 min )associated with a common sense amplifier (10). One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.

公开(公告)号：BR9001126A

公开(公告)日：1991-03-05

申请号：BR9001126

申请日：1990-03-09

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

IPC: G06F12/16 ,  G06F11/10 ,  G11C29/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：AU4939990A

公开(公告)日：1990-09-13

申请号：AU4939990

申请日：1990-02-09

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

IPC: G06F12/16 ,  G06F11/10 ,  G06F12/00 ,  G06F11/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：AU1436576A

公开(公告)日：1977-12-01

申请号：AU1436576

申请日：1976-05-27

Applicant: IBM

Inventor： KALTER HOWARD LEO

IPC: G11C11/419 ,  G11C11/409 ,  G11C11/4091 ,  H03K3/353 ,  G11C11/24 ,  G11C11/40 ,  G11C7/06

Abstract: A high speed ratioless FET sense amplifier for sensing stored information in a semiconductor memory system. The amplifier is capable of sensing very small voltage signals provided by charges stored in a plurality of single FET/capacitor memory cells. The amplifier comprises a pair of cross-coupled FET devices coupled to a pair of bit/sense lines by clock signal responsive switching devices. The source electrodes of the cross-coupled FETs are each independently capacitively coupled to another clock signal and also to a source of low potential through a pair of clock driven source pull-down FETs. The amplifier uses minimal size devices and is process parameter independent.

公开(公告)号：DE2642303A1

公开(公告)日：1977-04-07

申请号：DE2642303

申请日：1976-09-21

Applicant: IBM

Inventor： FURMAN ANATOL ,  KALTER HOWARD LEO ,  NAGEL JOHANN WERNER

IPC: H01L27/10 ,  G11C11/24 ,  G11C11/35 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/07 ,  H01L27/088 ,  H01L27/108 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L29/76

Abstract: Semiconductor integrated circuits, including, e.g., field effect transistors and memory cells employing field effect transistors, are formed by providing at a surface of semiconductor substrate a pair of isolation mediums and a plurality of spaced apart conductive lines extending between the isolation mediums. The conductive lines, such as polycrystalline silicon or polysilicon lines, are preferably thermally, chemically or anodically self insulatable in an unmasked batch process step and are made of a material suitable for defining a barrier to a dopant for the semiconductor substrate. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium made of a dual dielectric, such as silicon dioxide-silicon nitride, the dopant may be ion implanted through the insulating medium to form, e.g., the source and drain electrodes of the transistors as defined by the isolation mediums and the conductive lines. Other elements may be added to the structure to form, e.g., a memory cell. By depositing a conductive medium over the insulated conductive lines, the medium may be appropriately etched to provide desired access lines, capacitor electrodes, ground planes or additional field shields for the cells.