公开(公告)号：JPH11297812A

公开(公告)日：1999-10-29

申请号：JP34271998

申请日：1998-12-02

Applicant: IBM ,  TOSHIBA CORP

Inventor： MANDELMAN JACK A ,  MORIKADO MUTSUO ,  HO HERBERT ,  JEFFREY P GANBINO

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To inhibit the formation of a recessed part and to prevent the large change of threshold voltage and off current, by previously removing a nitride liner on the upper part of a side wall with shallow trench element separation. SOLUTION: Resist 17 is etched to the depth of 1000 Å from the surface of a silicon substrate by chemical dry etching(CDE). A silicon nitride liner 16a at the upper part of a shallow trench 14 is removed and whole resist 17a in the shallow trench 14 is removed by CDE. TEOS oxide is embedded in the shallow trench 14, and shallow element separation is formed. A pad nitride film 13 and a pad oxide film 12 on a separated element area are removed, and a gate oxide film and a gate electrode are formed. A source area and a drain area are formed by ion implanting and MOSFET is completed. At the time of removing the pad nitride film 13, a recessed part by the removal of the silicon nitride liner is not formed since the silicon nitride liner is not exposed to a surface.

公开(公告)号：JPH11260935A

公开(公告)日：1999-09-24

申请号：JP4799

申请日：1999-01-04

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a cap self-aligned on a gate conductor, and realize a two actional function for selectively applying P doping and N doping to the gate conductor. SOLUTION: A selected number of gate structures having self-aligned insulating layers 2 and 4 are doped by a first conductive type dopant through at least one sidewall of the gate structure. Thus, one gate structure is doped with the first conductive dopant, and another gate structure is doped with a second and different conductive dopant in this gate structural array. Therefore, a two actional function can be given.

公开(公告)号：JPH10256551A

公开(公告)日：1998-09-25

申请号：JP3989398

申请日：1998-02-23

Applicant: IBM

Inventor： DONALD C WHEELER ,  JEFFLE P GANVINO ,  LEWIS L TSU ,  MANDELMAN JACK A ,  REBECCA D MI

IPC: H01L21/027 ,  H01L21/266 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a new FET (asymmetrical field effect transistor) with improved reliability and performance. SOLUTION: An asymmetrical field effect transistor includes a first region 54 to be a source, a second region 53 to be a drain, a thin gate oxide 52 and a gate electrode 51. The gate electrode is asymmetrical and one of its side wall is sloped. The second region 53 extends under the sloped side wall 56. The part of the second region 53 extending under the gate electrode 51 is doped more lightly than the rest of the second region 53. The second region 53 is further provided with a sloped junction edge 58 under the gate electrode 51.

公开(公告)号：JP2004193596A

公开(公告)日：2004-07-08

申请号：JP2003396240

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  BAIE XAVIER ,  MANDELMAN JACK A ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a field-effect transistor whose charge carrier mobility increases by the stress of an electric current channel 22.
SOLUTION: The direction of the stress is that in which a current flows (vertical direction). For a PFET device, the stress is compressive stress, while the stress is tensile stress in an NFET device. The stress is produced by a compressive film 34 located in an area 32 under the channel. The compressive film pushes up the channel 22 which bends the channel. In the PFET device, the compressive film is arranged under the edge 31 of the channel (e.g., under a source or drain) which compresses the upper part 22A of the channel. In the NFET device, the compressive film is arranged under the center 40 of the channel (e.g., under the gate) which pulls the upper part 22A of the channel. Therefore, both the NFET device and the PFET device can be strengthened. A method for manufacturing these devices is included.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004128494A

公开(公告)日：2004-04-22

申请号：JP2003325279

申请日：2003-09-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BYONJU PAKU ,  MANDELMAN JACK A ,  FURUKAWA TOSHIHARU

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78621 ,  H01L29/78636

Abstract: PROBLEM TO BE SOLVED: To provide a multi-mesa FET structure having a doped sidewall for a source/drain region and its forming method. SOLUTION: This method makes use of the fact that when using a doping method which does not depend on a geometric shape such as a vapor doping or a plasma doping, a uniform doping of the whole sidewall is obtained by exposing the source and the drain sidewall during manufacturing. As a result, a device manufactured can have a large quantity of current per unit area of a silicon because it has a threshold voltage and a current density that does not depend on the depth and controlled with accuracy, and also its mesa quantity is extremely high compared with a mesa which can be formed by a conventional technology. Instead of a normal subtractive etching method, a multi-mesa FET structure forming method using a Damascene method gate process or a Damascene method alternate gate process is included. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004040095A

公开(公告)日：2004-02-05

申请号：JP2003178790

申请日：2003-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK A ,  RAMACHANDORA DEIVAKARUNI ,  YANG HAINING

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10864 ,  H01L27/10888 ,  H01L27/10891

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM array employing a small vertical transistor of bitline capacitance. SOLUTION: A DRAM array comprising DRAM cells employing the vertical transistor increases electrical reliability and reduces the bitline capacitance by the use of an asymmetric structure in connection between a wordline 310 and the transistor. Thereby, the DRAM array permits the use of wider connection between the wordline 310 and a transistor electrode. Also, the word line 310 is used as an etch stop to protect a transistor gate 205 during the patterning of the wordline 310. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003273235A

公开(公告)日：2003-09-26

申请号：JP2003053740

申请日：2003-02-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MANDELMAN JACK A ,  FILIPPI RONALD G ,  JEFFREY P GANBINO ,  RICHARD A WAKNICK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/60 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L27/08

CPC classification number: H01L21/76897 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/5286 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with interconnected conductor lines.
SOLUTION: The semiconductor device includes a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines surrounded by an insulator formed on the lower ILD layer are formed on the top surface of the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and the set is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on an upper level. Each of the upper conductor lines has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供配备有互连的导线的半导体器件。 解决方案：半导体器件包括具有形成在衬底上的顶表面的下层间介电层（ILD）层。 在下部ILD层的上表面形成有由下部ILD层形成的绝缘体围绕的多个下部导体线。 一组电阻螺柱中的每一个具有侧壁，下端和上端，并且该组在下端处连接到下导体线的顶部。 在通过衬垫层和电容器电介质层从相邻螺柱分离的电阻螺柱之间形成几个中间导体线。 上导线形成在上层。 每个上导体线具有与相应的一个电阻螺柱接触的底表面。 中间ILD层覆盖中间导体，用于将中间导体线与上导体线电绝缘和分离。 版权所有（C）2003，JPO

公开(公告)号：JP2002134631A

公开(公告)日：2002-05-10

申请号：JP2001300150

申请日：2001-09-28

Applicant: IBM

Inventor： ADKISSON JAMES W ,  RAMACHANDORA DEIVAKARUNI ,  JEFFREY P GANBINO ,  MANDELMAN JACK A

IPC: H01L27/10 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that comprises an embedded DRAM device and a logic device, and to provide a its manufacturing method. SOLUTION: This device comprises a monocrystal substrate having an almost flat surface, a first surface region on the flat surface having a silicon on insulator region, a second surface region on the flat surface which is a monocrystal bulk region, an embeded logic device which is formed in the silicon on insulator region, an embedded memory device which is formed in the monocrystal bulk region, and a trench in the bulk monocrystal region.

公开(公告)号：JP2001068672A

公开(公告)日：2001-03-16

申请号：JP2000210075

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  JEFFREY P GANBINO ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To obtain an improved structure and a production process of semiconductor device, e.g. MOSFET, in which possibility of thermal shrinkage and permeation of boron are reduced. SOLUTION: A sacrificial oxide layer 1 and a polysilicon/silicon nitride film are deposited sequentially on a substrate 2, an opening is made therein by etching (at the part of 5, 15) and ions are implanted in order to suppress hot carriers 11 thus suppressing punch through 8 between source and drain. After it is filled with a gate insulation film 12, a polysilicon layer 14 and a tungsten layer 15, upper part of an implanted part 18 for extending the source-drain is opened by etching, a spacer 19 is formed therein and contact implantation appropriate to P or N type is carried out. Thereafter, a nitride etch barrier layer 20 is formed, a contact region 21 is opened and filled with a polysilicon layer 22.

公开(公告)号：JP2000232210A

公开(公告)日：2000-08-22

申请号：JP2000017633

申请日：2000-01-26

Applicant: IBM

Inventor： LEWIS L SUU ,  DAVID E KOTEKKI ,  MANDELMAN JACK A

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a ferroelectric capacitor which is annealed before formation of a bit line and formed on an active region for the purpose of reducing the size of a memory cell. SOLUTION: This integrated circuit structure is provided with at least a transistor structure, a ferroelectric capacitor 5 of transistor structure, and a conductive circuit 70 located between the transistor structure and the ferroelectric capacitor 50. The ferroelectric capacitor 50 is annealed before the conductive contact 70 is formed.