公开(公告)号：WO2007082227A3

公开(公告)日：2008-09-25

申请号：PCT/US2007060317

申请日：2007-01-10

Applicant: IBM ,  CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory (100) having multiple ports per memory cell for accessing a data bit with each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plural of capacitors (102) connected together as a unitary source of capacitance (S). A first access transistor (104) is coupled between a firs one of the plurality of capacitors and a first bitline (RBL) and a second access transistor (106) is coupled between a second one of th plurality of capacitors and a second bitline (WBL) In each memory cell, a gate of the first access transistor (104) is connected to a fi wordline (RWL) and a gate of the second access transistor (106) is connected to a second wordline (WWL)

Abstract translation: 提供一种集成电路，其包括每个存储器单元具有多个端口的存储器（100），用于利用多个存储器单元中的每一个访问数据位。 这样的存储器包括存储单元阵列，其中每个存储单元包括连接在一起的多个电容器（102）作为电容（S）的整体源。 第一存取晶体管（104）耦合在所述多个电容器中的第一个电容器中，并且第一位线（RBL）和第二存取晶体管（106）耦合在所述多个电容器中的第二电容器和第二位线（WBL ）在每个存储单元中，第一存取晶体管（104）的栅极连接到fi字线（RWL），第二存取晶体管（106）的栅极连接到第二字线（WWL）

公开(公告)号：JP2004193588A

公开(公告)日：2004-07-08

申请号：JP2003389984

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEWIS L SUU ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: G11C11/412 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM cell design capable of simultaneously attaining high performance, low power, and small chip size by using only vertical MOSFET device including a peripheral (transmission) gate. SOLUTION: A method for forming a SRAM cell device comprises the steps of forming a pass gate FET transistor in a silicon layer formed on a flat insulating material and a parallel island, and further forming a pair of vertical pulldown FET transistors having a first common body and a first common source region. The method further forms a pulldown separation space for dividing an upper layer of a pullup and pulldown drain region of a pair of vertical pulldown FET transistor in two by etching through the upper diffusion between cross-linked inverter FET transistors, and the separation space reaches the common boby layer. The method further comprises the steps of forming a pair of vertical pullup FET transistor having a second common body and a second common drain, and connecting the FET transistor so as to form a SRAM cell. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：通过仅使用包括外围（传输）门的垂直MOSFET器件，提供能够同时获得高性能，低功率和小芯片尺寸的SRAM单元设计。 解决方案：一种用于形成SRAM单元器件的方法包括以下步骤：在形成于平坦绝缘材料和平行岛上的硅层中形成栅极FET晶体管，并进一步形成一对垂直下拉FET晶体管，其具有 第一共同体和第一共同源区。 该方法进一步形成一个下拉分离空间，用于通过在交联的反相FET晶体管之间的上部扩散进行蚀刻，将一对垂直下拉式FET晶体管的上拉和下拉漏极区的上层分成两层，分离空间达到 普通boby层。 该方法还包括以下步骤：形成具有第二公共体和第二公共漏极的一对垂直上拉FET晶体管，并连接FET晶体管以形成SRAM单元。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2003023155A

公开(公告)日：2003-01-24

申请号：JP2002127052

申请日：2002-04-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS L ,  RADENS CARL J ,  SHEPARD JOSEPH F JR

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET(metal oxide semiconductor field effect transistor) and a method for manufacturing the MOSFET capable of eliminating the overlap of a gate dielectric and a source/drain region with high reliability.
SOLUTION: This method for manufacturing a MOSFET comprises the process of patterning a gate laminate constituted of a gate dielectric 20 arid a gate conductor 30 formed on a substrate 10, and the process of modifying the gate dielectric 20 beneath the gate dielectric 30 so that the gate dielectric 20 can have a central portion and a modified dielectric region 70 adjacent to the central portion. The modified dielectric region 70 has a lower dielectric constant than that of the gate dielectric 20, and the central portion is shorter than the gate conductor 30.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种MOSFET（金属氧化物半导体场效应晶体管）以及能够以高可靠性消除栅极电介质和源极/漏极区域的重叠的MOSFET的制造方法。 解决方案：用于制造MOSFET的方法包括对由栅极电介质20和形成在衬底10上的栅极导体30构成的栅极叠层的图案化以及在栅极电介质30下面改变栅极电介质20的工艺， 栅极电介质20可以具有与中心部分相邻的中心部分和改进的电介质区域70。 改性电介质区域70具有比栅极电介质20低的介电常数，并且中心部分比栅极导体30短。

公开(公告)号：JP2000058795A

公开(公告)日：2000-02-25

申请号：JP21248499

申请日：1999-07-27

Applicant: SIEMENS AG ,  IBM

Inventor： SHEN HUA ,  NUETZEL JOACHIM ,  RADENS CARL J ,  KOTECKI DAVID

IPC: H01G4/12 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To maintain an appropriate height of a lower part electrode while the surface region of the lower part electrode for a stacked capacity is improved, by forming a first electrode electrically combined to a conductive access path and then forming a second electrode on a dialectics layer formed on the first electrode. SOLUTION: A tapered surface 122 in a trench 116 is formed as a conical part in the trench 116. A lower part electrode (first electrode) 124 is formed on the upper surface comprising a side wall 118 (and the tapered surface 122) by deposition of a metal layer 126, for example, such noble metal as platinum (Pt). A high dielectric constant layer 134 is formed on the metal layer 126. The metal layer 126 forms a lower part electrode of a stacked capacitor. An upper part electrode (second electrode) 136 is formed by deposition of a conductive material above the high dielectric constant layer 134 in the trench 116. The upper part electrode 136 is prefered to be formed of platinum, while such a conductive material as iridium(Ir), for example, may be used.

公开(公告)号：JP2000012801A

公开(公告)日：2000-01-14

申请号：JP14714699

申请日：1999-05-26

Applicant: IBM ,  SIEMENS AG

Inventor： ECONOMIKOS LAERTIS ,  GRUENING ULRIKE ,  HO HERBERT L ,  RADENS CARL J ,  JAMMY RAGARAO ,  HOEPFNER JOACHIM ,  SHEN HUA

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned collar and a buried plate while forming a reliable node dielectrics on the collar without requiring a plurality of independent trench recesses for forming the buried plate and the collar. SOLUTION: Etching for a trench is made within a surface of a semiconductor substrate 10 and a dielectric material layer is formed on a side wall 12 of the trench. The dielectric material layer is partially eliminated to expose a lower base region of the upper part of the trench side wall 12. After that an oxide layer is made to grow on the upper part of the side wall 12. The dielectric layer is eliminated from a remaining part of the side wall 12 and a buried plate 17 is formed by doping. The dielectric layer includes the upper part of the collar and a node, (i,e, the trench wall at a portion of the buried plate 17) and is provided for the trench wall. An inner electrode 19 is formed at the inner part of the trench.

公开(公告)号：JP2003133317A

公开(公告)日：2003-05-09

申请号：JP2002193642

申请日：2002-07-02

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  RADENS CARL J ,  WANG LI-KONG ,  WONG KEITH KWONG HON

IPC: G03F7/40 ,  H01B13/00 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H05K3/02

Abstract: PROBLEM TO BE SOLVED: To provide a more simplified substitutional method of the conventional damascene approach. SOLUTION: The cloisonne approach includes a step of coating a semiconductor substrate with a photosensitive polymer, such as pyrrole having a silver salt, aniline, etc. A conductive polymer is exposed to a wet developing solution, by using standard photolithography and the resists developing method and only conductive polymer wires are left on a substrate by removing part of the exposed conductive polymer region. Then an insulating dielectric layer is adhered to the whole structure, and conductive polymer wires are produced by planarizing an insulator by the chemical mechanical polishing (CMP). Another embodiment of this invention includes a method and structure for a self- planarizing interconnecting material containing the conductive polymer. Consequently, the number of treating steps can be reduced, as compared with the conventional technology.

公开(公告)号：JP2002305287A

公开(公告)日：2002-10-18

申请号：JP2002016927

申请日：2002-01-25

Applicant: IBM

Inventor： MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal-oxide film semiconductor integrated circuit which contains a notched gate in a support device region, and to provide a method of forming the integrated circuit. SOLUTION: A gate stack 16 is formed on a substrate, a patterned mask 24 is formed on the gate stack, the stack gate is etched by using the mask, and rather than the entire part but a part of a gate conductor is removed. A gap-filling film 28 is formed on the whole face, and the gap-filling film is removed in such a way that the gap filling film is left between masked gate stacks in an array device region. A spacer is formed on the exposed sidewall of the masked gate stack, and the exposed gate conductor inside the array device region and inside the support device region is removed. An undercut is formed in the lower exposed part of the remaining gate conductor. The remaining gap filling film is removed from the masked protective gate stack inside the array device region.

公开(公告)号：JP2002222873A

公开(公告)日：2002-08-09

申请号：JP2001388866

申请日：2001-12-21

Applicant: IBM

Inventor： RAMACHANDORA DEIVAKARUNI ,  LEE HEON ,  MANDELMAN JACK A ,  RADENS CARL J ,  SIM JAI-HOON

IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108 ,  H01L29/772

Abstract: PROBLEM TO BE SOLVED: To provide an improved method of forming a vertical MOSFET structure. SOLUTION: A method of forming a semiconductor memory cell array structure comprises a process of providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer 22 planarized up to the top surface of a trench top oxide 24 on a silicon substrate, a process of forming a recess 39 in the gate conductor layer below the top surface of the silicon substrate, a process of forming doping pockets 46 in an array P well 32 by implanting N-type dopant species through the recess at an angle, a process of forming spacers 44 on the side wall of the recess by depositing an oxide layer in the recess and then etching the oxide layer, and a process of depositing a gate conductor material in the recess and then planarizing the gate conductor material up to the top surface of the trench top oxide.

公开(公告)号：JP2001007223A

公开(公告)日：2001-01-12

申请号：JP2000160941

申请日：2000-05-30

Applicant: IBM

Inventor： JEFFREY P GANBINO ,  LEWIS L SUU ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a dual work function gate conductor having a self-aligned insulating cap, and a method for forming the dual work function gate conductor. SOLUTION: Two diffusion regions 36 are formed on a substrate 20, and gate stacks 33 and 34 are formed on the substrate 20 between these regions 36. The stacks 33 and 34 have a gate insulating layer 24, and polysilicon layers 26 and 26a on the layer 24, respectively. The layers 26 and 26a are n-type doped and remain intrinsic. A barrier layer 28 is formed on each of the layers 26 and 26a. A dopant source 30 is formed on the layer 28 for both stacks 33 and 34. The layer 28 has a p-type dopant. The stacks 33 and 34 are covered with an insulating cap 32 so that diffusion contacts can be formed on the gates in a borderless manner. When to start activating the source 30 for doping the layers 26 and 26a can be postponed until the desired timing.

公开(公告)号：JP2000091525A

公开(公告)日：2000-03-31

申请号：JP25944099

申请日：1999-09-13

Applicant: IBM

Inventor： JAMMY RAJARAO ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor memory structure, especially a deep trench semiconductor memory device for which a temperature sensitive high dielectric constant material is taken inside the storage node of a capacitor. SOLUTION: In this manufacturing method, after shallow trench separation at high temperature and processing a gate conductor, a deep trench storage capacitor is manufactured. With the manufacturing method, a temperature sensitive high dielectric constant material can be taken into a capacitor structure without causing decomposition of the material. Furthermore, the manufacturing method limits the spread of a buried strap outward diffused part 44, and thus the electric characteristics of an array MOSFET are improved.