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    31.
    发明专利
    未知

    公开(公告)号：DE10056830A1

    公开(公告)日：2002-05-29

    申请号：DE10056830

    申请日：2000-11-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

    IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  G11C11/14

    Abstract: The invention relates to an integrated magnetoresistive semiconductor memory system, in which n memory cells that comprise two magnetic layers (WML, HML), each separated by a thin dielectric barrier (TL), and associated word lines (WL) and bit lines (BL) that cross one another are vertically stacked in n layers (L1, L2, L3, L4). The system further comprises a decoding circuit for selecting one of the n memory layers (L1 - L4). Said decoding circuit, on both ends of a word line (WL) or a bit line (BL), is provided with one arrangement each that consists of n layer selecting transistors (N0 - N3, N4 - N7) for selecting one of the n memory layers (L1 - L4), and with a line selection transistor (P0, P1) for selecting the respective horizontal word line or bit line (WL or BL) on which a voltage (V) is to be impressed.

    32.
    发明专利
    未知

    公开(公告)号：DE59803426D1

    公开(公告)日：2002-04-25

    申请号：DE59803426

    申请日：1998-12-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  OTANI DR ,  SCHLOESSER DR ,  WEINRICH DR ,  RUSCH ANDREAS ,  TRUEBY ALEXANDER ,  HAIN MANFRED ,  ZIMMERMANN DR ,  KOHLHASE DR

    IPC: H01L21/8247 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

    Abstract: The memory cell arrangement has several ferroelectric memory cells (S) provided in a semiconductor substrate (10). Parallel bit line grooves (1a-1e) run in the longitudinal direction in the main surface of the substrate. A bit line (15a-15d) is provided in the base of each groove. A source drain region (25a-25d) is provided at the ridge of each groove. A channel region is provided in the walls of each groove. The channel regions are provided in one groove wall, such that a controllable switching transistor for selecting the respective memory cell is formed, while the channel region in the other wall is arranged such that the respective transistor is off. Insulated word lines are provided in the transverse direction along the main surface of the substrate through the bit line grooves, to control the selection transistors. Insulation grooves (3a-3c) run in the transverse direction in the main surface of the substrate to insulate the source/drain regions of adjacent memory cells. A ferroelectric capacitor is connected to each source/drain region of respective memory cell (s) above the word lines (2a-2d).

    34.
    发明专利
    未知

    公开(公告)号：DE10005618A1

    公开(公告)日：2001-08-30

    申请号：DE10005618

    申请日：2000-02-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LAMMERS STEFAN ,  MANYOKI ZOLTAN ,  HOENIGSCHMID HEINZ ,  BOEHM THOMAS

    IPC: G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

    Abstract: An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

    36.
    发明专利
    未知

    公开(公告)号：DE50004329D1

    公开(公告)日：2003-12-11

    申请号：DE50004329

    申请日：2000-03-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  MANYOKI ZOLTAN ,  ROEHR THOMAS

    IPC: G11C11/401 ,  G11C7/14 ,  G11C11/22

    Abstract: The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.

    37.
    发明专利
    未知

    公开(公告)号：DE59903679D1

    公开(公告)日：2003-01-16

    申请号：DE59903679

    申请日：1999-09-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROEHR THOMAS ,  BOEHM THOMAS ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG

    IPC: G11C11/409 ,  G11C7/12 ,  G11C7/22 ,  G11C11/22

    Abstract: The memory has writable memory cells. In addition, it has a bit line pair which connects the memory cells MC to a differential sense amplifier. A control unit is used for precharging the bit lines in a plurality of steps before one of the memory cells is conductively connected to one of the bit lines for a read access operation. For a write access operation, the control unit carries out no more than some of the bit line precharging steps provided for a read access operation before the sense amplifier transfers data to the bit line pair.

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