公开(公告)号：DE10051909B4

公开(公告)日：2007-03-22

申请号：DE10051909

申请日：2000-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AHLERS DIRK ,  DETZEL THOMAS ,  FRIZA WOLFGANG ,  RUEB MICHAEL

IPC: H01L29/06 ,  H01L29/40

公开(公告)号：DE10239312B4

公开(公告)日：2006-08-17

申请号：DE10239312

申请日：2002-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUEB MICHAEL ,  STRACK HELMUT

IPC: H01L21/331 ,  H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861

公开(公告)号：DE10066053B4

公开(公告)日：2006-03-30

申请号：DE10066053

申请日：2000-12-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEBER HANS ,  AHLERS DIRK ,  STENGL JENS-PEER ,  DEBOY GERALD ,  WILLMEROTH ARMIN ,  RUEB MICHAEL ,  CUADRON MARION MIGUEL

IPC: H01L29/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

公开(公告)号：DE10239312A1

公开(公告)日：2004-03-25

申请号：DE10239312

申请日：2002-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUEB MICHAEL ,  STRACK HELMUT

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/331 ,  H01L29/08 ,  H01L29/739 ,  H01L29/861 ,  H01L21/336 ,  H01L29/78

Abstract: Production of semiconductor component with drift zone (23) of first conductivity connected to field stop layer (20) of first conductivity more strongly doped than drift zone comprises preparing semiconductor layer having base doping and exposed front side (101), and introducing dopants of second conductivity via front side into drift zone region from front side to prescribed depth which is lower than semiconductor layer thickness. Production of a semiconductor component with a drift zone (23) of a first conductivity and a field stop layer (20) of a first conductivity more strongly doped than the drift zone and connected to it comprises preparing a semiconductor layer having a base doping and an exposed front side (101), and introducing doping atoms of a second conductivity via the front side into a drift zone region which extends from the front side up to a prescribed depth which is lower than the thickness of the semiconductor layer. An Independent claim is also included for a semiconductor component produced by the above process.

公开(公告)号：DE10260644B3

公开(公告)日：2004-03-18

申请号：DE10260644

申请日：2002-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUEB MICHAEL

IPC: H01L21/265 ,  H01L21/268

Abstract: Doping a semiconductor body (1, 2) comprises implanting doping centers of the ions (6) producing a conducting type in the semiconductor body, and heat treating using ion radiation so that doping of the conducting type prevails in the semiconductor body. Further heat treatment is carried out in determined regions in the semiconductor body at a higher temperature than that of the first heat treatment.

公开(公告)号：DE10239868A1

公开(公告)日：2004-03-18

申请号：DE10239868

申请日：2002-08-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUEB MICHAEL

IPC: H01L21/261 ,  H01L21/331 ,  H01L29/06 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78

Abstract: Production of column regions (S) having a first conductivity type (n) in semiconductor wafers comprises depositing alternating n-doped and p-doped epitaxial layer sections (11, 12) on a semiconductor substrate (10), forming a topology step in or on the epitaxial layers (12), and converting the p-doped layers into n-doped layer sections using high energy implantation. Independent claims are also included for the following: (1) Trench transistor arrangement containing the doped column regions; and (2) Transistor array containing trench transistor arrangements.

公开(公告)号：DE10121181A1

公开(公告)日：2002-11-14

申请号：DE10121181

申请日：2001-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUEB MICHAEL

IPC: H01L21/266

Abstract: Stencil mask (1) has implantation openings (2) in a substrate through which the implantation energy is projected onto a wafer. The critical mass of the openings is defined depending on each implantation energy. An Independent claim is also included for a process for the production of the stencil mask comprising depositing or growing a first pre-structured oxide layer on the silicon side of a wafer, and trench etching the silicon layer. Preferred Features: The stencil mask is based on a SOI base material.

公开(公告)号：DE10061310A1

公开(公告)日：2002-06-27

申请号：DE10061310

申请日：2000-12-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEBER HANS ,  AHLERS DIRK ,  STENGL JENS-PEER ,  DEBOV GERALD ,  WILLMEROTH ARMIN ,  RUEB MICHAEL ,  MARION MIGUEL CUADRON

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739

Abstract: The device has an active structure and an edge structure with edge compensation areas and floating edge compensation areas with edge compensation zones. Certain areas are fully depleted of charge carriers before reaching breakdown voltage. The compensation field strength in the edge structure is lower than that in an active area. The device has an active structure (AS) with a blocking pn-junction in a semiconducting substrate, a first zone (6) of a first conductor type connected to a first electrode (S) and bounding on a zone of opposite type forming the junction blocking zone (7) also connected to the first electrode, a second zone (1) of first type connected to a second electrode (D) and compensation areas (3') nested between the first and second zones. An edge structure (RS) has a number of first edge compensation areas (2) of the first type and a number of floating edge compensation areas (3) of the second type with edge compensation zones (4) and nested with the first areas so that the second areas are fully depleted of charge carriers before reaching the breakdown voltage. The compensation field strength in the edge structure is lower than that in an active area. Independent claims are also included for the following: a method of manufacturing a semiconducting component.

公开(公告)号：DE10006523A1

公开(公告)日：2001-08-23

申请号：DE10006523

申请日：2000-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUEB MICHAEL ,  LEHMANN VOLKER ,  TIHANYI JENOE

IPC: H01L21/266 ,  H01L29/06

Abstract: The invention relates to a re-usable implantation mask (5), preferably made of silicon, comprising specially structured trenches and holes(2 or 3), which is provided directly or at a distance from a device wafer (7). The invention also relates to a method for adjusting a further processing plane on an implantation plane in a semiconductor wafer (7) fitted with one such implementation mask.