IMPLANTATION MASK FOR HIGH ENERGY ION IMPLANTATION
    1.
    发明申请
    IMPLANTATION MASK FOR HIGH ENERGY ION IMPLANTATION 审中-公开
    注入掩模高能离子注入

    公开(公告)号:WO0161735A3

    公开(公告)日:2002-07-18

    申请号:PCT/DE0100596

    申请日:2001-02-15

    CPC classification number: H01L29/0634 H01L21/266

    Abstract: The invention relates to a re-usable implantation mask (5), preferably made of silicon, comprising specially structured trenches and holes(2 or 3), which is provided directly or at a distance from a device wafer (7). The invention also relates to a method for adjusting a further processing plane on an implantation plane in a semiconductor wafer (7) fitted with one such implementation mask.

    Abstract translation: 本发明涉及一种可重复使用的注入掩模(5)配有特定图案的沟槽和孔制成优选硅(2或3),其直接或在器件晶片(7),以及用于在注入电平调整一个进一步的处理面的方法的距离设置 一个具有这样的注入掩模的半导体晶片(7)处理。

    2.
    发明专利
    未知

    公开(公告)号:DE102005046427A1

    公开(公告)日:2007-04-05

    申请号:DE102005046427

    申请日:2005-09-28

    Abstract: A power transistor has a source region, a drain region, a semiconductor body arranged between the source region and the drain region, and a plurality of nanotubes. The plurality of nanotubes are connected in parallel and disposed in the semiconductor body such that the plurality of nanotubes are electrically insulated from the semiconductor body and electrically connect the source and drain regions of the transistor. The power transistor also includes at least one diode formed in the semiconductor body. A portion of the at least one diode formed in the semiconductor body is configured to act as a gate electrode for the transistor.

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