公开(公告)号：AU2003267005A1

公开(公告)日：2004-03-29

申请号：AU2003267005

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  SPECHT MICHAEL ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.

公开(公告)号：AU2003264084A8

公开(公告)日：2004-03-29

申请号：AU2003264084

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LANDGRAF ERHARD ,  SCHULZ THOMAS ,  SPECHT MICHAEL ,  HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/115 ,  H01L29/73 ,  H01L29/76 ,  H01L29/792

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F 2 per bit can thus be achieved.

公开(公告)号：AU2003264084A1

公开(公告)日：2004-03-29

申请号：AU2003264084

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  SPECHT MICHAEL ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/115 ,  H01L29/73 ,  H01L29/76 ,  H01L29/792

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F 2 per bit can thus be achieved.

公开(公告)号：DE10227605A1

公开(公告)日：2004-01-15

申请号：DE10227605

申请日：2002-06-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN R JOHANNES ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  KRETZ JOHANNES

IPC: H01L21/8242 ,  H01L25/065 ,  H01L21/58 ,  H01L21/283 ,  H01L27/108 ,  H01L27/112

Abstract: A layer system comprises a substrate having a surface processed with a conductive metal structure and an opposite processed second surface. A second substrate is attached by a third surface to the first surface of the first substrate. An independent claim is also included for a process for producing the system above.

公开(公告)号：DE10213545A1

公开(公告)日：2003-10-23

申请号：DE10213545

申请日：2002-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  GOETTSCHE RALF ,  PACHA CHRISTIAN ,  STEINHOEGL WERNER

IPC: H01L27/08 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786

公开(公告)号：DE10030391C2

公开(公告)日：2003-10-02

申请号：DE10030391

申请日：2000-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTWICH JESSICA ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/786 ,  H01L21/283

公开(公告)号：DE10145699A1

公开(公告)日：2003-04-10

申请号：DE10145699

申请日：2001-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ATTI MASSIMO ,  SCHULZ THOMAS ,  HARTWICH JESSICA ,  LUYKEN JOHANNES R

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L21/84

Abstract: Layer arrangement comprises a crystalline substrate (101) made from a first semiconductor material; trenches (102, 103) inserted into the substrate with a part of the trench being filled with an electrically insulating material; and crystalline sections (106, 107) made from a second semiconductor material applied on the first semiconductor material via a part of the trench. An Independent claim is also included for a process for the production of the layer arrangement. Preferred Features: The first and second semiconductor materials are made from silicon, germanium, or a silicon-germanium alloy. The arrangement further comprises an electronic component integrated on or in the substrate. The crystalline section and the substrate are electrically decoupled from each other. The arrangement further comprises a source region, a drain region, a channel region, a gate oxide region and a gate region.

公开(公告)号：DE19928564A1

公开(公告)日：2001-01-04

申请号：DE19928564

申请日：1999-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROESNER WOLFGANG ,  SCHULZ THOMAS ,  RISCH LOTHAR ,  FRANOSCH MARTIN

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/788

Abstract: A dual-gate MOSFET semiconductor layer structure is constructed on a substrate (1). Said semiconductor layer structure consists of a first gate electrode and a second gate electrode (10A, 10B), between which a semiconductor channel layer area (4A) is embedded, and a source area (2A) and a drain area (2B), which are situated on opposite front sides of the semiconductor channel layer area (4A). At least one other semiconductor channel layer area (6A) is provided at one of the gate electrodes (10B), the front sides of this semiconductor channel layer area (6A) also being contacted by the source (2A) and drain (2B) areas.

公开(公告)号：DE102010016164B4

公开(公告)日：2020-12-03

申请号：DE102010016164

申请日：2010-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  ZANDEN KOEN VAN DER

IPC: H01L27/115 ,  H01L27/11517

Abstract: Floating-Gate-Speicherbauelement (110), aufweisend:ein Substrat (210);ein über dem Substrat (210) angeordnetes Floating Gate (230); undein Steuergate (250), das mindestens einen Teil des Floating Gate (230) lateral vollständig umgibt und über einer oberen Oberfläche (232) des Floating Gate (230) angeordnet ist.

公开(公告)号：DE102010016164A1

公开(公告)日：2010-12-30

申请号：DE102010016164

申请日：2010-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  ZANDEN KOEN VAN DER

IPC: H01L27/115

Abstract: Eine oder mehrere Ausführungsformen betreffen ein Floating-Gate-Speicherbauelement (110), aufweisend: ein Substrat (210); ein über dem Substrat (210) angeordnetes Floating Gate (230); und ein Steuergate (250), das mindestens einen Teil des Floating Gate (230) im Wesentlichen lateral umgibt.