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    31.
    发明专利
    未知

    公开(公告)号：DE69808190T2

    公开(公告)日：2003-05-28

    申请号：DE69808190

    申请日：1998-07-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： JAOUEN HERVE ,  MARTY MICHEL

    IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L27/10 ,  H01L29/92 ,  H01L21/3205

    Abstract: Production of a metal-metal capacitor within an IC is carried out by forming the two metal electrodes (40, 71) and the dielectric layer (61) on the lower insulating layer (2) bearing a metallisation level (M1) of the IC before depositing the upper insulating layer (80) for covering the metallisation level (M1). Also claimed is an IC including a metal-metal capacitor (40, 61, 71) produced as described above. Preferably, the first capacitor electrode (40) is part of the metallisation level (preferably aluminium), the second electrode (70, 71) is a thinner layer preferably of aluminium or tungsten and the dielectric layer (61) is a thin SiO2, Si3N4 or Ta2O5 layer.

    33.
    发明专利
    未知

    公开(公告)号：FR2779573A1

    公开(公告)日：1999-12-10

    申请号：FR9807061

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  REGOLINI JORGE LUIS

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/737 ,  H01L29/732

    Abstract: The bipolar transistor comprises a base (Be) of heterojunction silicon-germanium. The base is in block (8) of layers of silicon and silicon-germanium on an initial layer (17) of silicon nitride spread on a region with lateral isolation (5). An internal collector (4) is enclosed and situated inside a window in the layer of silicon nitride. The fabrication process includes the growth of a layer of silicon dioxide on a block of semiconductor. A layer of silicon nitride (Si3N4) is then deposited, and etched until the layer of silicon dioxide. A chemical process is used to remove a portion of the layer of silicon dioxide within the window. The layer of silicon nitride has a thickness of about 300 Angstrom, and that of silicon dioxide about 200 Angstrom.

    34.
    发明专利
    未知

    公开(公告)号：FR2779572A1

    公开(公告)日：1999-12-10

    申请号：FR9807059

    申请日：1998-06-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

    Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

    39.
    发明专利
    未知

    公开(公告)号：DE60307174D1

    公开(公告)日：2006-09-14

    申请号：DE60307174

    申请日：2003-05-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  CREMER SEBASTIEN ,  MARTY MICHEL

    IPC: H01L21/02 ,  H01L23/522

    Abstract: Capacitor is manufactured in substrate (1) by digging recess into substrate; forming first conformal layer of insulating material; forming second conductive layer; forming third layer of conductive or insulating material filling up recess; digging trenches into third layer, across entire height; depositing fourth layer of conductive material; forming fifth layer of dielectric material; and depositing sixth layer of conductive material. An Independent claim is also included for a capacitor formed in a substrate comprising: (a) a recess (2) dug into a substrate; (b) a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; (c) a second layer of a conductive material covering the first layer; (d) a third layer of a conductive or insulating material filling the recess; (e) trenches crossing the third layer; (f) a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges; (g) a fifth layer of a dielectric material covering the fourth layer; and (h) a sixth layer of a conductive material covering the fifth layer.

    40.
    发明专利
    未知

    公开(公告)号：FR2858877A1

    公开(公告)日：2005-02-18

    申请号：FR0350418

    申请日：2003-08-11

    Applicant: ST MICROELECTRONICS SA

    Inventor： MARTINET BERTRAND ,  MARTY MICHEL ,  CHEVALIER PASCAL ,  CHANTRE ALAIN

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737

    Abstract: A method for forming a heterojunction bipolar transistor including the steps of: forming in a semiconductor substrate a collector area of a first doping type; growing by epitaxy above a portion of the collector area a silicon/germanium layer of a second doping type forming a base area; forming above the silicon/germanium layer a sacrificial emitter formed of a material selectively etchable with respect to the silicon/germanium layer and with respect to the layers and consecutively-formed insulating spacers; forming first insulating spacers on the sides of the sacrificial emitter; growing by epitaxy a silicon layer above the exposed portions of the silicon/germanium layer; forming second insulating spacers adjacent to the first spacers and laid on the silicon layer; covering the entire structure with an insulating layer; partially removing the insulating layer above the sacrificial emitter and removing the sacrificial emitter; filling the space previously taken up by the sacrificial emitter with a semiconductor material of the first doping type.

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