公开(公告)号：FR2857150A1

公开(公告)日：2005-01-07

申请号：FR0307960

申请日：2003-07-01

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  CANDELLIER PHILIPPE ,  CERUTTI ROBIN ,  CORONEL PHILIPPE ,  MAZOYER PASCALE

IPC: G11C11/405 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  G11C11/401 ,  H01L21/8242

Abstract: The unit has a pair of cells (C1, C2) for storing two independent bits and including field effect transistors with grid (4, 14), respectively. A channel is arranged in a source zone (102), and the two transistors are arranged in between the source zone and a drain zone. An electrode of single polarization (24) is arranged between intermediate portions (1, 11) of the two transistors. An independent claim is also included for a method for manufacturing an integrated DRAM on a surface of a substrate.

公开(公告)号：FR2845522A1

公开(公告)日：2004-04-09

申请号：FR0212278

申请日：2002-10-03

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  CORONEL PHILIPPE ,  LEVERD FRANCOIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/732 ,  H01L21/74

Abstract: An integrated circuit incorporates a buried layer of the type with conductivity determined in a plane essentially parallel to a plane of a main surface of the circuit. The median part of this buried layer (23, 24) is filled with a metallic type material (29). An Independent claim is also included for a method for the formation of a layer buried in a semiconductor substrate of an integrated circuit.

公开(公告)号：FR2844396A1

公开(公告)日：2004-03-12

申请号：FR0302772

申请日：2003-03-06

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： BUSTOS JESSY ,  CORONEL PHILIPPE ,  REGNIER CHRISTOPHE ,  WACQUANT FRANCOIS ,  TAVEL BRICE ,  SKOTNICKI THOMAS

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: The production of an electronic component consists of: (a) covering the surface (S) of a substrate (100) with a portion (P) delimiting with the substrate a volume (V) filled at least partially with a temporary material; (b) evacuating the temporary material from the volume by a shaft (C) extending between the volume and an access surface; (c) introducing an electrical conducting filling material (7) into the volume from some precursors fed via the shaft. Independent claims are also included for: (1) a field effect transistor with a gate produced by this method; (2) an electronic device incorporating such a transistor.

公开(公告)号：FR2905519A1

公开(公告)日：2008-03-07

申请号：FR0653524

申请日：2006-08-31

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

Inventor： CORONEL PHILIPPE ,  MARTY MICHEL

IPC: H01L21/8236 ,  H01L27/088

Abstract: L'invention concerne un procédé de fabrication d'un circuit intégré contenant des transistors MOS complètement et partiellement déplétés, comprenant les étapes suivantes .a) former des transistors MOS similaires sur une couche mince de silicium (3) formée sur une couche de silicium-germanium (2) reposant sur un substrat de silicium ;b) coller la face supérieure de la structure à une plaquette support (21) ;c) éliminer le substrat;d) déposer un masque (23) et ouvrir ce masque aux emplacements des transistors complètement déplétés ;e) oxyder le silicium-germanium aux emplacements des transistors complètement déplétés dans des conditions telles qu'il se produit un phénomène de condensation ; etf) éliminer la partie oxydée et la partie de silicium-germanium, d'où il résulte qu'il demeure des transistors dont la couche de silicium est amincie.

公开(公告)号：FR2904143A1

公开(公告)日：2008-01-25

申请号：FR0653082

申请日：2006-07-24

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS CROLLES 2

Inventor： CAZAUX YVON ,  CORONEL PHILIPPE ,  FENOUILLET BERANGER CLAIRE ,  ROY FRANCOIS

IPC: H01L27/146 ,  H04N3/15

Abstract: L'invention concerne un capteur d'images comprenant des cellules photosensibles comportant des photodiodes (D) et au moins un circuit supplémentaire à forte dissipation thermique comportant des transistors (M7, M8). Le capteur d'images est réalisé de façon monolithique et comprend une couche (60) d'un matériau semiconducteur ayant des première et deuxième faces opposées (15, 16) et comprenant, du côté de la première face (15), des premières régions (34, 38) correspondant aux bornes de puissance des transistors, l'éclairage du capteur d'images étant destiné à être réalisé du côté de la deuxième face ; un empilement de couches isolantes (70) recouvrant la première face ; un renfort (78) thermiquement conducteur recouvrant l'empilement du côté opposé à la couche ; et des vias (76) thermiquement conducteurs reliant la couche au renfort.

公开(公告)号：FR2844396B1

公开(公告)日：2006-02-03

申请号：FR0302772

申请日：2003-03-06

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： BUSTOS JESSY ,  CORONEL PHILIPPE ,  REGNIER CHRISTOPHE ,  WACQUANT FRANCOIS ,  TAVEL BRICE ,  SKOTNICKI THOMAS

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: The production of an electronic component consists of: (a) covering the surface (S) of a substrate (100) with a portion (P) delimiting with the substrate a volume (V) filled at least partially with a temporary material; (b) evacuating the temporary material from the volume by a shaft (C) extending between the volume and an access surface; (c) introducing an electrical conducting filling material (7) into the volume from some precursors fed via the shaft. Independent claims are also included for: (1) a field effect transistor with a gate produced by this method; (2) an electronic device incorporating such a transistor.

公开(公告)号：FR2830124B1

公开(公告)日：2005-03-04

申请号：FR0112377

申请日：2001-09-26

Applicant: ST MICROELECTRONICS SA

Inventor： PIAZZA MARC ,  CORONEL PHILIPPE

IPC: H01L21/8242 ,  H01L27/108

Abstract: A method for forming in monolithic form a DRAM-type memory, including the steps of forming, on a substrate, parallel strips including a lower insulating layer, a strongly-conductive layer, a single-crystal semiconductor layer, and an upper insulating layer; digging, perpendicularly to the strips, into the upper insulating layer and into a portion of the semiconductor layer, first and second parallel trenches, each first and second trench being shared by neighboring cells; forming, in each first trench, a first conductive line according to the strip width; forming, in each second trench, two second distinct parallel conductive lines, insulated from the peripheral layers; filling the first and second trenches with an insulating material; removing the remaining portions of the upper insulating layer; and depositing a conductive layer.

公开(公告)号：FR2853454A1

公开(公告)日：2004-10-08

申请号：FR0304143

申请日：2003-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  MORAND YVES ,  SKOTNICKI THOMAS ,  CERUTTI ROBIN

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A MOS transistor formed in a silicon substrate (101) comprises: (a) an active zone (100) surrounded by an insulating partition (102); (b) a first conducting strip (103) covering a central strip of the active zone; (c) one or more second conducting strips (105, 106, 107) placed in the active zone plumb with the first strip; (d) some conducting regions (108, 109) placed in two cavities in the insulating partition and joined to the ends of the first and second strips; (e) the surfaces of the silicon opposite the strips and conducting regions are covered with an insulator (130) constituting an oxide grid. An independent claim is also included for the production of this MOS transistor.

公开(公告)号：FR2848724A1

公开(公告)日：2004-06-18

申请号：FR0215837

申请日：2002-12-13

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE

IPC: H01L21/68 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L23/535

Abstract: The production of connections buried in an integrated circuit comprises: (a) providing a structure made up of a first support slice stuck in the rear surface of a thin semiconductor slice, one or more integrated circuit elements possibly being realised in or above the thin slice; (b) sticking a second support slice on the structure at the side of the leading surface of the thin slice; (c) eliminating the first support slice; (d) forming some connections between the different zones of the rear surface of the thin slice; (e) sticking a third support slice on the connections; and (f) eliminating the second support slice. An Independent claim is also included for an integrated circuit incorporating some components and produced by the above process.

公开(公告)号：FR2982424B1

公开(公告)日：2014-01-10

申请号：FR1160209

申请日：2011-11-09

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： MONFRAY STEPHANE ,  SAVELLI GUILLAUME ,  SKOTNICKI THOMAS ,  CORONEL PHILIPPE ,  GAILLARD FREDERIC

IPC: H01L37/00

Abstract: Système de conversion d'énergie thermique en énergie électrique (S1) destiné à être disposé entre une source chaude (SC) et une source froide (SF) , comportant des moyens de conversion de l'énergie thermique en énergie mécanique (6) et un matériau piézoélectrique, les moyens de conversion de l'énergie thermique en énergie mécanique (6) comportant des groupes (G1, G2 ) de au moins trois bilames (9, 11, 13) reliés mécaniquement entre eux par leur extrémités longitudinales et suspendus au-dessus d'un substrat (12), chaque bilame (9, 11, 13) comportant deux états stables dans lesquels il présente dans chacun des états une courbure, deux bilames directement adjacentes (9, 11, 13) présentant pour une température donnée des courbures opposées, le passage d'un état à stable des bilames (9, 11, 13) à l'autre provoquant la déformation d'un matériau piézoélectrique.