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    33.
    发明专利
    未知

    公开(公告)号：DE69418037D1

    公开(公告)日：1999-05-27

    申请号：DE69418037

    申请日：1994-08-02

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L21/60 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L29/72

    Abstract: In a MOS-technology power device chip and package assembly, the MOS-technology power device chip (1) comprises a semiconductor material layer (4,5) in which a plurality of elementary functional units (6) is integrated, each elementary functional unit (6) contributing for a respective fraction to an overall current and comprising a first doped region (7) of a first conductivity type formed in said semiconductor layer (4,5), and a second doped region (10) of a second conductivity type formed inside said first doped region (7); the package (2) comprises a plurality of pins (P1-P10) for the external electrical and mechanical connection; said plurality of elementary functional units (6) is composed of sub-pluralities of elementary functional units (6), the second doped regions (10) of all the elementary functional units (6) of each sub-plurality being contacted by a same respective metal plate (100) electrically insulated from the metal plates (100) contacting the second doped regions (10) of all the elementary functional units (6) of the other sub-pluralities; each of said metal plate (100) is connected, through a respective bonding wire (W1-W5), to a respective pin (P1-P5) of the package (2).

    37.
    发明专利
    未知

    公开(公告)号：DE69434937D1

    公开(公告)日：2007-04-19

    申请号：DE69434937

    申请日：1994-06-23

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

    IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

    Abstract: A zero thermal budget process for the manufacturing of a MOS-technology vertical power device (such as a MOSFET or a IGBT) comprises the steps of: forming a conductive Insulated gate layer (8) on a surface of a lightly doped semiconductor material layer (3) of a first conductivity type; selectively removing the insulated gate layer (8) from selected portions of the semiconductor material layer (3) surface; selectively implanting a first dopant of a second conductivity type into said selected portions of the semiconductor material layer (3), the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, heavily doped regions (5) substantially aligned with the edges of the insulated gate layer (8); selectively implanting a second dopant of the second conductivity type along directions tilted of prescribed angles ( alpha 1, alpha 2) with respect to a direction orthogonal to the semiconductor material layer (3) surface, the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, lightly doped channel regions (6) extending under the insulated gate layer (8); selectively implanting a heavy dose of a third dopant of a first conductivity type into the heavily doped regions (5), to form source regions (7) substantially aligned with the edges of the insulated gate layer (8).

    38.
    发明专利
    未知

    公开(公告)号：DE69833743T2

    公开(公告)日：2006-11-09

    申请号：DE69833743

    申请日：1998-12-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRISINA FERRUCCIO

    IPC: H01L29/06 ,  H01L21/336 ,  H01L29/78

    Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, comprising a first step of forming a first semiconductor layer (41) of a first conductivity type, a second step of forming a first mask (37) over the top surface of the first semiconductor layer (41), a third step of removing portions of the first mask (37) in order to form at least one opening (51) in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer (41) through the at least one opening (51), a fifth step of completely removing the first mask (37) and of forming a second semiconductor layer (42) of the first conductivity type over the first semiconductor layer (41), a sixth step of diffusing the dopant implanted in the first semiconductor layer (41) in order to form a doped region (220) of the second conductivity type in the first and second semiconductor layers (41, 42). The second step up to the sixth step are repeated at least one time in order to form a final edge structure comprising a number of superimposed semiconductor layers (41, 42, 43, 44, 45, 46) of the first conductivity type and at least two columns of doped regions (220, 230, 240, 250, 260) of the second conductivity type, the columns being inserted in the number of superimposed semiconductor layers (41, 42, 43, 44, 45, 46) and formed by means of superimposition of the doped regions (220, 230, 240, 250, 260) subsequently implanted through the mask openings, the column near the high voltage semiconductor device being deeper than the column farther to the high voltage semiconductor device.

    40.
    发明专利
    未知

    公开(公告)号：DE69631524T2

    公开(公告)日：2004-10-07

    申请号：DE69631524

    申请日：1996-07-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAGRI ANGELO ,  ZAMBRANO RAFFAELE ,  FRISINA FERRUCCIO

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

    Abstract: A MOS technology power device comprises a semiconductor substrate (1), a semiconductor layer (2) of a first conductivity type superimposed over the semiconductor substrate (1), an insulated gate layer (5,6,7;51,52,6,7) covering the semiconductor layer (2), a plurality of substantially rectilinear elongated openings (10) parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes (3) of a second conductivity type formed in the semiconductor layer (2) under the elongated openings (10), source regions (4) of the first conductivity type included in the body stripes (3) and a metal layer (9) covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions (31) substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion (31) including a source region (4) extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions (32), longitudinally intercalated with the first portions (31), substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions (31) and second portions (32) of the body stripes (3) being respectively aligned in a direction transversal to the longitudinal axis.

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