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    31.
    发明专利
    未知

    公开(公告)号：ITTO990994A1

    公开(公告)日：2001-05-16

    申请号：ITTO990994

    申请日：1999-11-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

    IPC: G11C5/14 ,  G11C11/56 ,  G11C16/30

    Abstract: The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

    32.
    发明专利
    未知

    公开(公告)号：ITMI20002018D0

    公开(公告)日：2000-09-15

    申请号：ITMI20002018

    申请日：2000-09-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  TORELLI GUIDO ,  MANSTRETTA ALESSANDRO

    IPC: G11C7/06 ,  G11C16/28

    Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, at least one differential amplifier connected at the input of the first and the second nodes and having an output terminal to provide a logic signal correlated to the selected cell information, a first voltage-controlled discharge switch circuit connected to the first node and to a voltage reference, a second switch circuit connected to the second node and the voltage reference, and first and second voltage comparator circuits receiving the first selected cell voltage and the second reference cell voltage.

    34.
    发明专利
    未知

    公开(公告)号：DE602005017113D1

    公开(公告)日：2009-11-26

    申请号：DE602005017113

    申请日：2005-12-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  CAIMI CARLO ,  MASTRODOMENICO GIOVANNI

    IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

    Abstract: Flash NAND memory electronic device comprising non-volatile cells and having a high integration density and relative programming method. Memory device (1) of the type integrated on a semiconductor substrate (3) and comprising one matrix (6) with rows or Word lines (4) and columns or Bit lines (5) organised in sectors (7) of memory cells (2). The device (1) comprising between said cells (2) of said opposite Word lines (4) belonging to at least one of said sectors (7) of said matrix (6) a lateral coating (15) along the direction of the Bit lines (5) having at least one conductive layer (16) with a contact terminal (9) being selectively biased or floating during each program, read or erase operation, each cell belonging to said sector (7).

    35.
    发明专利
    未知

    公开(公告)号：DE60139670D1

    公开(公告)日：2009-10-08

    申请号：DE60139670

    申请日：2001-04-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GREGORI STEFANO ,  MICHELONI RINO ,  PIERIN ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO

    IPC: G11C16/02 ,  G11C16/12 ,  G11C11/56

    Abstract: The method involves applying in succession, to a control terminal of the memory cell, at least two programming pulse trains (F1,F2) with pulse amplitude increasing in staircase fashion. The amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Transition from the first programming pulse to train to the second is made when the memory cell has a threshold voltage with a pre-set relation with a reference value.

    36.
    发明专利
    未知

    公开(公告)号：DE60227534D1

    公开(公告)日：2008-08-21

    申请号：DE60227534

    申请日：2002-11-18

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： KHOURI OSAMA ,  BEDESCHI FERDINANDO ,  RESTA CLAUDIO

    IPC: G11C11/34 ,  G11C7/04 ,  G11C16/02

    Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor (20) of chalcogenic material furnishing an electrical quantity (V(T), I(T)) that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed (21) so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor (20) has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

    38.
    发明专利
    未知

    公开(公告)号：DE69927364D1

    公开(公告)日：2005-10-27

    申请号：DE69927364

    申请日：1999-07-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  SACCO ANDREA ,  PICCA MASSIMILIANO

    IPC: G11C16/06 ,  G11C5/14 ,  G11C8/10 ,  G11C8/00

    Abstract: The memory device (10) comprises a memory array (2) having an organisation of the type comprising global word lines (4) and local word lines (6), a global row decoder (8) addressing the global word lines (4), a local row decoder (12) addressing the local word lines (6), a global power supply stage (22) supplying the global row decoder (8), and a local power supply stage (24) supplying the local row decoder (12).

    40.
    发明专利
    未知

    公开(公告)号：IT1320699B1

    公开(公告)日：2003-12-10

    申请号：ITTO20000936

    申请日：2000-10-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  GREGORI STEFANO ,  KHOURI OSAMA ,  TORELLI GUIDO

    IPC: G11C11/56 ,  G11C16/26 ,  G11C16/30

    Abstract: A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).

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