公开(公告)号：IT1213260B

公开(公告)日：1989-12-14

申请号：IT2412684

申请日：1984-12-18

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78 ,  C07C

Abstract: The disclosed bridge circuit is fabricated using power MOS technology. Common terminals of the bridge circuit are integrated into common regions in the implementation. Electrodes, typically coupled together in the bridge circuit, are implemented by a shared conducting region in the integrated circuit of the semiconductor chip. By integrating the elements of the circuit, less area of the semiconductor chip is required as compared to an implementation involving 4 (four) discrete elements. Diodes are fabricated across the transistors to protect the elements against reverse biasing.

公开(公告)号：ITUB20161081A1

公开(公告)日：2017-08-25

申请号：ITUB20161081

申请日：2016-02-25

Applicant: ST MICROELECTRONICS SRL

Inventor： TOIA FABRIZIO FAUSTO RENZO ,  CONTIERO CLAUDIO ,  PIZZI ELISABETTA ,  MARIANI SIMONE DARIO

IPC: H01L21/74 ,  H01L23/535

公开(公告)号：DE69528961D1

公开(公告)日：2003-01-09

申请号：DE69528961

申请日：1995-03-09

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  PALMIERI MICHELE

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8247 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L27/115 ,  H01L29/08 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

公开(公告)号：DE69415987T2

公开(公告)日：1999-06-24

申请号：DE69415987

申请日：1994-11-08

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  DEPETRO RICCARDO

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/41

Abstract: An integrated device presenting a structure for protection against electric fields. The protection structure is formed by a first region of conducting material (34) connected electrically to the gate/source region (6) of the device and at a first potential, and by a second region of conducting material (35) connected electrically to the drain region (15) of the device and at a second potential differing from the first. The first region of conducting material (34) is comb-shaped, and presents a first number of fingers (32) separated by a number of gaps; and the second region of conducting material (35) presents portions (33) extending at the aforementioned number of gaps and also forming a comb structure, so that the body of semiconductor material (1) of the device sees a protection region formed by a pair of interlocking comb structures and at an intermediate potential between the first and second potentials.

公开(公告)号：DE69505348T2

公开(公告)日：1999-03-11

申请号：DE69505348

申请日：1995-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： DE PETRO RICCARDO ,  PALMIERI MICHELE ,  GALBIATI PAOLA ,  CONTIERO CLAUDIO

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: A high voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication. To save area of silicon and to reduce the specific resistivity RDS on enriched drain regions (16) are formed by implanting doping material (N) in the silicon through apertures in the field oxide (11) obtained with a selective anisotropic etching by utilising as a mask the strips of polycrystaline silicon (14) which serve as gate electrodes and field electrodes.

公开(公告)号：DE69528961T2

公开(公告)日：2003-09-04

申请号：DE69528961

申请日：1995-03-09

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  PALMIERI MICHELE

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8247 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L27/115 ,  H01L29/08 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

公开(公告)号：DE69330564T2

公开(公告)日：2002-06-27

申请号：DE69330564

申请日：1993-12-15

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  MANZINI STEFANO ,  CAVIONI TIZIANA

IPC: H01L21/8247 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L27/088

Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area (18) formed by the same operations as are necessary to form a P region (17) intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are necessary to form the source and drain regions (31) of said transistor, a control electrode (15) consisting of an N+ region formed by the same operations as are carried out to form deep regions (14) intended to contact buried N+ regions, and a floating gate electrode (24) consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes (23) of the MOS transistors in the integrated circuit. The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

公开(公告)号：DE69330564D1

公开(公告)日：2001-09-13

申请号：DE69330564

申请日：1993-12-15

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  MANZINI STEFANO ,  CAVIONI TIZIANA

IPC: H01L21/8247 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L27/088

Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area (18) formed by the same operations as are necessary to form a P region (17) intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are necessary to form the source and drain regions (31) of said transistor, a control electrode (15) consisting of an N+ region formed by the same operations as are carried out to form deep regions (14) intended to contact buried N+ regions, and a floating gate electrode (24) consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes (23) of the MOS transistors in the integrated circuit. The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

公开(公告)号：DE69505348D1

公开(公告)日：1998-11-19

申请号：DE69505348

申请日：1995-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： DE PETRO RICCARDO ,  PALMIERI MICHELE ,  GALBIATI PAOLA ,  CONTIERO CLAUDIO

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: A high voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication. To save area of silicon and to reduce the specific resistivity RDS on enriched drain regions (16) are formed by implanting doping material (N) in the silicon through apertures in the field oxide (11) obtained with a selective anisotropic etching by utilising as a mask the strips of polycrystaline silicon (14) which serve as gate electrodes and field electrodes.

公开(公告)号：DE69315239T2

公开(公告)日：1998-03-19

申请号：DE69315239

申请日：1993-02-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  GALBIATI MARIA PAOLA ,  ZULLINO LUCIA

IPC: H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/772 ,  H01L29/08

Abstract: The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.