公开(公告)号：EP0943155A1

公开(公告)日：1999-09-22

申请号：EP98948810.0

申请日：1998-08-19

Applicant: ROBERT BOSCH GMBH

Inventor： LÄRMER, Franz ,  SCHILP, Andrea

IPC: H01L21 ,  B81C1

CPC classification number: B81C1/00619 ,  B81C2201/0112 ,  H01L21/30655

Abstract: The invention relates to a method for anisotropic etching of microstructures and nanostructures in silicon substrates by means of alternating consecutive independently controlled etching stages and stages in which polymer is deposited, whereby the amount of polymer deposited is reduced in the course of the deposit stages, thereby avoiding undercutting of the microstructures and nanostructures.

公开(公告)号：KR1020140052998A

公开(公告)日：2014-05-07

申请号：KR1020137030018

申请日：2012-05-09

Applicant: 램 리써치 코포레이션

Inventor： 위닉젝자로스로우더블유. ,  린프랭크와이. ,  밀러알란제이 ,  수,칭 ,  허성준 ,  함진환 ,  윤상준 ,  루수카멜리아

IPC: B81C1/00 ,  H01L21/3065 ,  C23F1/00

CPC classification number: H01L21/30655 ,  B81C1/00619 ,  B81C2201/0112 ,  H01L21/3086

Abstract: 동작 압력 및 동작 바이어스를 갖는 플라즈마 프로세싱 챔버에서 실리콘을 에칭하기 위한 방법이 제공된다. 방법은: 제 1 깊이 및 측벽을 갖는 홀을 생성하기 위해 실리콘에서 제 1 수직 에칭을 수행하는 단계; 측벽 상에서 보호층의 증착을 수행하는 단계; 홀을 제 2 깊이로 깊게 하고 제 2 측벽을 생성하기 위해 제 2 수직 에칭을 수행하는 단계로서, 제 2 측벽은 제 1 골, 제 2 골 및 피크를 포함하고, 제 1 골은 제 1 측벽에 대응하고, 제 2 골은 제 2 측벽에 대응하며, 피크는 제 1 골과 제 2 골 사이에 배치되는, 제 2 수직 에칭을 수행하는 단계; 및 피크를 감소시키기 위해 제 3 에칭을 수행하는 단계를 포함한다.

公开(公告)号：EP3356288A1

公开(公告)日：2018-08-08

申请号：EP16852584.8

申请日：2016-09-29

Applicant: Mems Drive Inc.

Inventor： GUTIERREZ, Roman ,  TANG, Tony ,  LIU, Xiaolei ,  WANG, Guiqin ,  NG, Matthew

IPC: B81B7/04 ,  B81B5/00 ,  B81B3/00

CPC classification number: H01L21/76816 ,  B81B3/0045 ,  B81B7/0029 ,  B81B2203/0353 ,  B81C1/00674 ,  B81C1/00682 ,  B81C2201/0112 ,  B81C2201/0135 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/485 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/181

Abstract: A system and method for manipulating the structural characteristics of a MEMS device include etching a plurality of holes into the surface of a MEMS device, wherein the plurality of holes comprise one or more geometric shapes determined to provide specific structural characteristics desired in the MEMS device.

公开(公告)号：EP2924000A4

公开(公告)日：2016-07-06

申请号：EP13857651

申请日：2013-11-01

Applicant: BEIJING NMC CO LTD

Inventor： JIANG ZHONGWEI

IPC: B81C1/00

CPC classification number: H01L21/32137 ,  B81C1/00531 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

公开(公告)号：EP2334589A1

公开(公告)日：2011-06-22

申请号：EP09787279.0

申请日：2009-09-24

Applicant: NXP B.V.

Inventor： ROOZEBOOM, Freddy ,  GOOSSENS, Martijn ,  BESLING, Willem Frederik Adrianus ,  VERHAEGH, Nynke

IPC: B81B1/00 ,  B81C99/00 ,  H01L29/41 ,  H01L31/0224

CPC classification number: H01L29/41 ,  B81B3/007 ,  B81B2201/06 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L28/91

Abstract: The invention relates to an semiconductor device comprising a first surface and neighboring first and second electric elements arranged on the first surface, in which each of the first and second elements extends from the first surface in a first direction, the first element having a cross section substantially perpendicular to the first direction and a sidewall surface extending at least partially in the first direction, wherein the sidewall surface comprises a first section and a second section adjoining the first section along a line extending substantially parallel to the first direction, wherein the first and second sections are placed at an angle with respect to each other for providing an inner corner wherein the sidewall surface at the inner corner is, at least partially, arranged at a constant distance R from a facing part of the second element for providing a mechanical reinforcement structure at the inner corner.

公开(公告)号：EP1099244B1

公开(公告)日：2007-01-24

申请号：EP99934921.0

申请日：1999-07-23

Applicant: SURFACE TECHNOLOGY SYSTEMS PLC

Inventor： BHARDWAJ, Jyoti, Kiron

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/3213

CPC classification number: B81C1/00619 ,  B01J12/007 ,  B01J19/2445 ,  B01J2219/00038 ,  B01J2219/0004 ,  B01J2219/00058 ,  B01J2219/00162 ,  B01J2219/0809 ,  B01J2219/0841 ,  B01J2219/0869 ,  B01J2219/0871 ,  B01J2219/0894 ,  B81C2201/0112 ,  C01B7/24 ,  C07C17/00 ,  H01L21/30621 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32135 ,  H01L21/32136

Abstract: There is disclosed a method of treating a substrate material or a film present on the material surface comprising cyclically performing the following steps: (a) etching the material or film; (b) depositing or forming a passivation layer on the surfaces of an etched feature; and (c) selectively removing the passivation layer from the etched feature in order that the etching proceeds in a direction substantially perpendicular to the material or film surface. At least one of the steps (a) or (b) is performed in the absence of a plasma. Also disclosed is an apparatus for performing the method.

公开(公告)号：EP0683921B1

公开(公告)日：2004-06-16

申请号：EP94903348.4

申请日：1993-12-03

Applicant: CORNELL RESEARCH FOUNDATION, INC.

Inventor： SHAW, Kevin, A. ,  ZHANG, Z., Lisa ,  MACDONALD, Noel, C.

IPC: H01L21/44 ,  H01L21/449 ,  H01L21/302 ,  H01L23/48 ,  H01L29/06 ,  H01L29/86 ,  H01L29/84 ,  H01L29/96

CPC classification number: B81C1/00619 ,  B81C1/00142 ,  B81C1/0015 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/053 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0817 ,  G01P2015/0828 ,  Y10S73/01 ,  Y10S148/05

Abstract: The invention provides a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation. A dielectric mask (12) on a single-crystal substrate (154) is patterned to define isolating trenches. A protective conformal layer (28) is applied to the resultant structure. The conformal layer (28) on the floor of the trenches is removed and a second etch deepens the trench to expose the mesa walls which are removed during the release step by isotropic etching. A metal layer (44) is formed on the resultant structure providing opposed plates (156) and (158) of a capacitor. The cantilever beam (52) with the supporting end wall (152) extends the grid-like structure (150) into the protection of the deepened isolation trenches (54). A membrane can be added to the released structures to increase their weight for use in accelerometers, and polished for use as movable mirrors.

公开(公告)号：EP3294664A1

公开(公告)日：2018-03-21

申请号：EP16725234

申请日：2016-05-09

Applicant: MURATA MANUFACTURING CO

Inventor： IIHOLA ANTTI ,  TORKKELI ALTTI ,  RYTKOENEN VILLE PEKKA ,  LIUKKU MATTI

IPC: B81B3/00

CPC classification number: B81B3/0021 ,  B81B3/0094 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0136 ,  B81B2203/04 ,  B81C1/00357 ,  B81C2201/0112 ,  B81C2201/0132

Abstract: The present invention relates to a micromechanical device comprising a multi-layer micromechanical structure including only homogenous silicon material. The device layer comprises at least a rotor and at least two stators. At least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a first surface of the device layer and at least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a second surface of the device layer.

公开(公告)号：EP2829512A1

公开(公告)日：2015-01-28

申请号：EP14177859.7

申请日：2014-07-21

Applicant: Atlantic Inertial Systems Limited

Inventor： Hawke, Tracey ,  Venables, Mark ,  Sturland, Ian ,  Eley, Rebecka

IPC: B81C1/00

CPC classification number: B81C1/00531 ,  B81B3/0064 ,  B81B2201/033 ,  B81B2203/033 ,  B81C1/00388 ,  B81C1/00619 ,  B81C2201/0112 ,  H01L21/3065 ,  H01L21/308

Abstract: A method of reactive ion etching a substrate 46 to form at least a first and a second etched feature (42, 44) is disclosed. The first etched feature (42) has a greater aspect ratio (depth:width) than the second etched feature (44). In a first etching stage the substrate (46) is etched so as to etch only said first feature (42) to a predetermined depth. Thereafter in a second etching stage, the substrate (46) is etched so as to etch both said first and said second features (42, 44) to a respective depth. A mask (40) may be applied to define apertures corresponding in shape to the features (42, 44). The region of the substrate (46) in which the second etched feature (44) is to be produced is selectively masked with a second maskant (50) during the first etching stage. The second maskant (50) is then removed prior to the second etching stage.

Abstract translation: 公开了一种反应离子蚀刻衬底46以形成至少第一和第二蚀刻特征（42,44）的方法。 第一蚀刻特征（42）具有比第二蚀刻特征（44）更大的纵横比（深度：宽度）。 在第一蚀刻阶段中，蚀刻衬底（46）以仅将所述第一特征（42）仅蚀刻到预定深度。 此后，在第二蚀刻阶段中，蚀刻衬底（46）以便将所述第一和第二特征（42,44）都蚀刻到相应的深度。 可以施加掩模（40）以限定形状对应于特征（42,44）的孔。 在第一蚀刻阶段期间，用第二掩模（50）选择性地掩蔽其中要产生第二蚀刻特征（44）的衬底（46）的区域。 然后在第二蚀刻阶段之前去除第二掩模（50）。

公开(公告)号：EP2539930A2

公开(公告)日：2013-01-02

申请号：EP11713021.1

申请日：2011-02-24

Applicant: SPP Process Technology Systems UK Limited

Inventor： DITIZIO, Robert

IPC: H01L21/768 ,  B81B1/00

CPC classification number: H01L21/76898 ,  B81B2207/07 ,  B81C1/00087 ,  B81C2201/0112 ,  H01L21/02118 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/3065 ,  H01L21/30655

Abstract: Vias are formed in a substrate using an etch process that forms an undercut profile below the mask layer. The vias are coated with a conformal insulating layer and an etch process is applied to the structures to remove the insulating layer from horizontal surfaces while leaving the insulating layers on the vertical sidewalls of the vias. The top regions of the vias are protected during the etchback process by the undercut hardmask.