-
公开(公告)号：JP2013509000A
公开(公告)日：2013-03-07
申请号：JP2012536802
申请日：2010-07-15
Applicant: ザイリンクス インコーポレイテッドXilinx Incorporated
Inventor： ワイランド，クリストファー・ピィ
CPC classification number: H01L23/66 , H01L23/64 , H01L2223/6616 , H01L2924/0002 , H01L2924/3011 , H05K1/0251 , H05K1/116 , H05K2201/09463 , H05K2201/09781 , H05K2201/09809 , H01L2924/00
Abstract: Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodiments of the present invention avoid impedance mismatch in circuits and achieve an advance in the art by providing a via with higher impedance through the addition of split ring resonators (SSRs) to each end of the via.
-
公开(公告)号：WO03104854A2
公开(公告)日：2003-12-18
申请号：PCT/US0318557
申请日：2003-06-11
Applicant: HAND HELD PROD INC
Inventor： HAVENS WILLIAM H , HENNICK ROBERT J , IZZO JOHN , ROBINSON MICHAEL
CPC classification number: G06K7/10584 , G06K7/10722 , G06K7/10801 , G06K7/10861 , G06K7/14 , H05K1/116 , H05K1/18 , H05K3/244 , H05K2201/09072 , H05K2201/09463 , H05K2201/0949 , H05K2201/09645 , H05K2201/09809 , H05K2201/10121
Abstract: An optical reader including an image sensor, imaging optics, a short range aiming assembly, and a long range aiming assembly. The short range aiming assembly may comprise a plurality of LEDs. The long range aiming assembly may comprise a laser diode assembly which projects an aiming pattern that is readily visible at reading distances of several feet. The optical reader can be configured so that long range aiming assembly is enabled or disabled depending upon a present operating condition.
Abstract translation: 包括图像传感器，成像光学元件，短距离瞄准组件和远程瞄准组件的光学读取器。 短距离瞄准组件可以包括多个LED。 长距离瞄准组件可以包括激光二极管组件，其投射在几英尺的读取距离处容易看见的瞄准图案。 光学读取器可以被配置为使得远程瞄准组件被启用或禁用，这取决于当前的操作条件。
-
公开(公告)号：WO2003102859A1
公开(公告)日：2003-12-11
申请号：PCT/US2003/017564
申请日：2003-06-04
Applicant: HAND HELD PRODUCTS, INC.
Inventor： HAVENS, William , BARBER, Charles, P. , GANNON, Colleen , GARDINER, Robert, C. , HENNICK, Robert, J. , PETTINELLI, John
IPC: G06K7/10
CPC classification number: G06K7/10881 , G06K7/10574 , G06K7/10584 , G06K7/10722 , G06K7/10801 , G06K7/10861 , G06K7/1098 , G06K7/14 , G06K7/1417 , H05K1/18 , H05K3/244 , H05K2201/09072 , H05K2201/09463 , H05K2201/0949 , H05K2201/09645 , H05K2201/09809 , H05K2201/10121
Abstract: The invention is an optical reader (5) having a plurality of imaging modules (10a, 10b). In one method for operating a multiple imaging module reader of the invention, a second frame of image data captured via actuation of a second imaging module is automatically captured and subjected to decoding in the case an attempt to decode using a frame of image data captured via actuation of a first imaging module fails. In another embodiment, a frame of image data captured via actuation of an image sensor of a first module and actuation of illumination of a second imaging module is subjected to decoding. In another embodiment, frames of image data captured via actuation of image sensors of spaced apart modules are combined. The various modules of a multiple imaging module reader can be adapted to have different best focus positions so that a field depth of the reader is improved.
Abstract translation: 本发明是具有多个成像模块（10a，10b）的光学读取器（5）。 在用于操作本发明的多成像模块读取器的一种方法中，通过第二成像模块的驱动捕获的第二帧图像数据被自动捕获，并且在尝试使用所捕获的图像数据的帧进行解码的情况下进行解码 第一成像模块的致动失败。 在另一个实施例中，经由第一模块的图像传感器的致动和第二成像模块的照明的致动所捕获的图像数据帧被进行解码。 在另一个实施例中，组合了通过间隔开的模块的图像传感器的致动捕获的图像数据帧。 多成像模块读取器的各种模块可以适于具有不同的最佳焦点位置，从而改善读取器的场深。
-
公开(公告)号：EP1983809B1
公开(公告)日：2018-09-12
申请号：EP08007057.6
申请日：2008-04-09
Applicant: YAZAKI CORPORATION
Inventor： Masaoki, Yoshida , Nakayama, Takuya , Ueyama, Koji
CPC classification number: H05K1/116 , H05K1/0256 , H05K3/3447 , H05K2201/09363 , H05K2201/09463 , H05K2201/0969 , H05K2201/09718 , H05K2201/10651 , H05K2203/1446
Abstract: The present invention is to provide a printed wiring board which can certainly prevent damage of conductive pattern caused by the terminal. The printed wiring board has a board, a conductive pattern, a through-hole and a non-conductive area. A lead wire of resistance mounted on the printed wiring board is inserted into the through-hole 4. The lead wire projects from a surface of the board, and is bent close to the surface. The non-conductive area is formed into a fan-shaped shape enlarging toward a tip of the lead wire from a center of the through-hole. Since the bent lead wire is arranged on the non-conductive area, the non-conductive area can prevent damage of the conductive pattern which is caused by touching the lead wire to the conductive pattern.
-
公开(公告)号：EP2494598A1
公开(公告)日：2012-09-05
申请号：EP10737421.7
申请日：2010-07-15
Applicant: Xilinx, Inc.
Inventor： WYLAND, Christopher, P.
IPC: H01L23/66
CPC classification number: H01L23/66 , H01L23/64 , H01L2223/6616 , H01L2924/0002 , H01L2924/3011 , H05K1/0251 , H05K1/116 , H05K2201/09463 , H05K2201/09781 , H05K2201/09809 , H01L2924/00
Abstract: Vias (106) are typically of a lower impedance than the signal lines (102, 128) connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. An embodiment avoids impedance mismatch in circuits and achieves an advance in the art by providing a via (106) with higher impedance through the addition of split ring resonators (104, 112, 120, 126) to each end of the via (106).
-
Patent Agency Ranking
公开(公告)号：EP1983809A3
公开(公告)日：2010-07-21
申请号：EP08007057.6
申请日：2008-04-09
Applicant: YAZAKI CORPORATION
Inventor： Masaoki, Yoshida , Nakayama, Takuya , Ueyama, Koji
IPC: H05K1/11
CPC classification number: H05K1/116 , H05K1/0256 , H05K3/3447 , H05K2201/09363 , H05K2201/09463 , H05K2201/0969 , H05K2201/09718 , H05K2201/10651 , H05K2203/1446
Abstract: The present invention is to provide a printed wiring board which can certainly prevent damage of conductive pattern caused by the terminal. The printed wiring board has a board, a conductive pattern, a through-hole and a non-conductive area. A lead wire of resistance mounted on the printed wiring board is inserted into the through-hole 4. The lead wire projects from a surface of the board, and is bent close to the surface. The non-conductive area is formed into a fan-shaped shape enlarging toward a tip of the lead wire from a center of the through-hole. Since the bent lead wire is arranged on the non-conductive area, the non-conductive area can prevent damage of the conductive pattern which is caused by touching the lead wire to the conductive pattern.
Abstract translation: 本发明提供一种能够可靠地防止由端子引起的导体图案的损伤的印刷布线板。 印刷线路板具有板，导电图案，通孔和非导电区域。 将安装在印刷线路板上的电阻引线插入到通孔4中。引线从电路板的表面突出，并弯曲靠近表面。 非导电区域形成为从通孔的中心向引线的末端扩大的扇形形状。 由于弯曲引线布置在非导电区域上，因此非导电区域可以防止由于引线接触导电图案而导致的导电图案的损坏。
-
37.发明公开Printed wiring board, semiconductor package, and printed circuit board with semiconductor package 审中-公开Leiterplatte，Halbleitergehäuse和und Leiterplatte mitHalbleitergehäuse
公开(公告)号：EP2658353A1
公开(公告)日：2013-10-30
申请号：EP13164422.1
申请日：2013-04-19
Applicant: Canon Kabushiki Kaisha
Inventor： Hayashi, Seiji , Kondo, Takuya , Matsumoto, Shoji
CPC classification number: H05K1/0216 , H01L23/49827 , H01L23/49838 , H01L2224/48227 , H05K1/0228 , H05K1/0242 , H05K1/0298 , H05K1/11 , H05K1/114 , H05K1/116 , H05K1/14 , H05K1/141 , H05K1/162 , H05K1/18 , H05K2201/0939 , H05K2201/09418 , H05K2201/09454 , H05K2201/09463 , H05K2201/09636 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734
Abstract: First (111) and second (112) signal wiring patterns are formed in a first conductor layer (101). A first electrode pad (121) electrically connected to the first signal wiring pattern through a first via (131) and a second electrode pad (122) electrically connected to the second signal wiring pattern through a second via (132) are formed in a second conductor layer (102) as a surface layer. A third conductor layer (103) is disposed between the first conductor layer and the second conductor layer with an insulator (105) interposed between those conductor layers. A first pad (141,151,161,171) electrically connected to the first via is formed in the third conductor layer. The first pad includes an opposed portion (141a,151b,161c,171d) which overlaps the second electrode pad as viewed in a direction perpendicular to the surface of a printed board and which is opposed to the second electrode pad through intermediation of the insulator. This enables reduction of crosstalk noise caused between the signal wirings.
Abstract translation: 在第一导体层（101）中形成第一（111）和第二（112）信号布线图案。 通过第二通孔（132）通过第一通孔（131）和与第二信号布线图案电连接的第二电极焊盘（122）电连接到第一信号布线图案的第一电极焊盘（121） 导体层（102）作为表面层。 第三导体层（103）设置在第一导体层和第二导体层之间，绝缘体（105）插入在这些导体层之间。 电连接到第一通孔的第一焊盘（141,151,161,171）形成在第三导体层中。 第一焊盘包括与垂直于印刷电路板的表面的方向观察的与第二电极焊盘重叠并且通过绝缘体与第二电极焊盘相对的相对部分（141a，151b，161c，171d）。 这能够减少在信号布线之间引起的串扰噪声。
-
38.发明公开Two-level mounting board and crystal oscillator using the same 审中-公开Zweistufen-Montageplatte und entsprechender Quarzoszillator
公开(公告)号：EP1919042A2
公开(公告)日：2008-05-07
申请号：EP07254214.5
申请日：2007-10-24
Applicant: Nihon Dempa Kogyo Co., Ltd.
Inventor： Ito, Manabu , Kuroda, Tomotaka , Uchida, Takeshi
IPC: H01R43/02
CPC classification number: H01R43/0256 , H01R12/52 , H05K1/141 , H05K3/3447 , H05K3/368 , H05K2201/09036 , H05K2201/09463 , H05K2201/10303 , H05K2201/1084 , H05K2201/10871 , H05K2203/1178 , Y10T428/24612
Abstract: The present invention relates to a two-level mounting board in which a second substrate is supported horizontally by a metal pin above a first substrate having a mounting electrode on an outer base surface, the free, lower end of the metal pin is inserted in a hole provided in the surface of the first substrate, and the metal pin is affixed by solder to an annular electrode land provided on the surface of the first substrate to form an outer periphery of the hole, wherein part of the ring of the annular electrode land is cut away to open the same. This provides a two-level mounting board in which metal pins can be connected reliably to the first substrate to support the second substrate horizontally, and a crystal oscillator using the same.
Abstract translation: 本发明涉及一种二级安装板，其中第二基板由位于外基座表面上的具有安装电极的第一基板上方的金属销水平支撑，金属销的自由下端插入 并且所述金属销通过焊料固定到设置在所述第一基板的表面上的环形电极焊盘，以形成所述孔的外周，其中所述环形电极的环的一部分 被切开打开一样。 这提供了一种两级安装板，其中金属引脚可以可靠地连接到第一基板以水平地支撑第二基板，以及使用其的晶体振荡器。
-
公开(公告)号：EP0341458A1
公开(公告)日：1989-11-15
申请号：EP89106941.1
申请日：1989-04-18
Applicant: PIONEER ELECTRONIC CORPORATION
CPC classification number: H05K3/3447 , H05K1/116 , H05K3/3415 , H05K3/3442 , H05K3/3468 , H05K3/4046 , H05K2201/09463 , H05K2201/0949 , H05K2201/09663 , H05K2201/099 , H05K2201/09909 , H05K2201/10651 , H05K2201/10689 , H05K2201/10939 , H05K2203/1178 , H05K2203/1476
Abstract: A double-sided board circuit includes a board (11) having insertion holes (12), a pair of electrically conductive patterns (15) disposed on the face and back of the board (11), and an electronic component (13) having directly connected electrically conductive wires (13a) inserted respectively through the insertion holes (12), at least one of the conductive wires being soldered at two positions to the conductive patterns (15) on the face and back of the board (11) to electrically connect the conductive patterns (15).
Abstract translation: 双面板电路包括具有插入孔（12）的基板（11），设置在基板（11）的表面和背面上的一对导电图案（15），以及电子部件（13），其具有直接 分别插入插入孔（12）中的至少一根导线被连接到板（11）的表面和背面上的导电图案（15）的两个位置处的电连接的导电线（13a）以电连接 导电图案（15）。
-
公开(公告)号：US09713264B2
公开(公告)日：2017-07-18
申请号：US14576107
申请日：2014-12-18
Applicant: Intel Corporation
Inventor： Brandon M. Rawlings , Henning Braunisch
CPC classification number: H05K3/0082 , H05K1/116 , H05K3/422 , H05K3/424 , H05K3/4647 , H05K3/4679 , H05K2201/09463 , H05K2201/09854 , H05K2203/0505
Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
-
-
-
-
-
-
-
-
-
Search Results
131
records
(took 0.032 seconds)
