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    A STRUCTURE AND IMPLEMENTATION METHOD FOR IMPLEMENTING AN EMBEDDED SERIAL DATA TEST LOOPBACK, RESIDING DIRECTLY UNDER THE DEVICE UNDER TEST WITHIN A PRINTED CIRCUIT BOARD
    43.
    发明公开
    A STRUCTURE AND IMPLEMENTATION METHOD FOR IMPLEMENTING AN EMBEDDED SERIAL DATA TEST LOOPBACK, RESIDING DIRECTLY UNDER THE DEVICE UNDER TEST WITHIN A PRINTED CIRCUIT BOARD 审中-公开
    用于实现在印刷电路板内部直接置于装置下的嵌入式串行数据测试回路的结构和实施方法

    公开(公告)号：EP3194989A1

    公开(公告)日：2017-07-26

    申请号：EP15835363.1

    申请日：2015-08-26

    Applicant: R&D Circuits Inc.

    Inventor： WARWICK, Thomas P. ,  RUSSELL, James V.

    IPC: G01R31/303

    CPC classification number: H04L1/243 ,  G01R31/2851 ,  G01R31/31716 ,  G01R31/31937 ,  H04L1/205 ,  H04L41/24 ,  H04L43/50 ,  H05K1/0231 ,  H05K1/185 ,  H05K2201/10015

    Abstract: A method and a structure with multiple implementations is provided that depends on the specific need, for placing (embedding) a serial loopback circuit of known design in a printed circuit board directly beneath the device under test. Micro-vias and traces connect components including transmitter components (TX) and receiver components (RX) that are formed into a loopback circuit for connection to a device under test (DUT). The connection is accomplished by a coupling capacitor with a shortest possible electrical length approximating a straight line between said components and said DUT and said distance is a length of said short straight line times a square root of 2 so that said receiver components are beneath the DUT.

    Abstract translation: 提供了一种具有多种实施方式的方法和结构，其取决于具体需要，用于将已知设计的串行环回电路放置（嵌入）到被测设备正下方的印刷电路板中。 微通孔和迹线连接包括发送器组件（TX）和接收器组件（RX）的组件，这些组件被形成为用于连接到被测器件（DUT）的回送电路。 该连接通过耦合电容器来实现，该耦合电容器具有接近所述组件和所述DUT之间的直线的可能的最短电长度，并且所述距离是所述短直线的长度乘以2的平方根，使得所述接收器组件位于DUT下方 。

    METHOD AND STRUCTURE FOR FORMING CONTACT PADS ON A PRINTED CIRCUIT BOARD USING ZERO UNDER- CUT TECHNOLOGY
    44.
    发明公开
    METHOD AND STRUCTURE FOR FORMING CONTACT PADS ON A PRINTED CIRCUIT BOARD USING ZERO UNDER- CUT TECHNOLOGY 审中-公开
    方法与结构接触表面上的电路板面平整使用零退刀技术

    公开(公告)号：EP2893783A1

    公开(公告)日：2015-07-15

    申请号：EP13834789.3

    申请日：2013-08-09

    Applicant: R&D Circuits Inc.

    Inventor： TURPUSEEMA, Dan ,  RUSSELL, James V

    IPC: H05K3/06 ,  H05K1/02 ,  H01L21/02

    CPC classification number: H05K3/425 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/427 ,  H05K2201/0959 ,  Y10T29/49156

    Abstract: A method and an apparatus for forming a contact pad on a printed circuit board over a filled plate via or blind in which an additional metallic or a non metallic coating is applied to a final surface finished plate which encapsulates the side walls of the wear resistant surface plate, and also covers the side walls of the metal layer plated onto the filled via and the wrap around plated metal which was plated in the via and onto the surface of the base metal to the extents of the pad geometry. This prevents subsequent undermining through the etching process and ensuring the integrity and reliability of the vias' electrical connection when an underlying base metal such as but not limited to copper and the surface plated metal are formed when plating metal in the via and consequently onto the surface.

    Abstract translation: 一种用于经由或盲在其中附加金属或非金属涂层在填充板形成的接触焊盘上的印刷电路板的方法和装置应用于最终表面成品板封装了耐磨表面的侧壁 板等覆盖经由镀在填充在金属层和周围的金属镀涡卷其在所述通孔和在基体金属到垫的几何形状的盘区的表面镀覆的侧壁上。 这防止随后通过蚀刻工艺破坏和确保通孔电当一个基础基部金属连接的完整性和可靠性：例如但不限于铜和表面镀覆金属形成当通过并因此在表面上的镀敷金属 ，

    IMPROVED POWER SUPPLY TRANSIENT PERFORMANCE (POWER INTEGRITY) FOR A PROBE CARD ASSEMBLY IN AN INTEGRATED CIRCUIT TEST ENVIRONMENT
    47.
    发明申请
    IMPROVED POWER SUPPLY TRANSIENT PERFORMANCE (POWER INTEGRITY) FOR A PROBE CARD ASSEMBLY IN AN INTEGRATED CIRCUIT TEST ENVIRONMENT 审中-公开
    用于集成电路测试环境中的探针卡组件的改进的电源瞬态性能（功率一体化）

    公开(公告)号：WO2016195766A1

    公开(公告)日：2016-12-08

    申请号：PCT/US2016/019865

    申请日：2016-02-26

    Applicant: R&D CIRCUITS, INC.

    Inventor： WARWICK, Thomas, P. ,  RUSSELL, James, V. ,  TURPUSEEMA, Dhananjaya

    IPC: G01R31/28

    CPC classification number: G01R31/2889 ,  G01R1/07378 ,  G01R31/31901 ,  G01R31/31905

    Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application, lit each embodiment, however, the critical improvement of this disclosure is the location of the passive components used, for supply filtering/ decoupling relative to prior art. All three embodiments, require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

    Abstract translation: 本发明基本上描述了实现针对芯片的低阻抗（过频）功率传递的三个不同实施例。 这种低阻抗到高频允许管芯以封装级速度工作，从而降低封装级别的产量损失。 每个实施例解决了每个实施例的整个晶片探针应用的略微不同的方面，然而，本公开的关键改进是所使用的无源部件的位置，用于相对于现有技术的电源滤波/去耦。 所有三个实施例都需要一种方法来将无源部件嵌入到靠近螺距平移基板的位置，或物理地嵌入螺距平移基板。

    STRUCTURE FOR ISOLATING HIGH SPEED DIGITAL SIGNALS IN A HIGH DENSITY GRID ARRAY
    48.
    发明申请
    STRUCTURE FOR ISOLATING HIGH SPEED DIGITAL SIGNALS IN A HIGH DENSITY GRID ARRAY 审中-公开
    在高密度网格阵列中分离高速数字信号的结构

    公开(公告)号：WO2015183797A1

    公开(公告)日：2015-12-03

    申请号：PCT/US2015/032409

    申请日：2015-05-26

    Applicant: R&D CIRCUITS, INC

    Inventor： WARWICK, Thomas, P.

    IPC: H01L23/58 ,  H01L23/485 ,  H05K9/00

    CPC classification number: H01L23/5225 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L2224/16225 ,  H05K1/0222 ,  H05K1/0243 ,  H05K1/113 ,  H05K1/116 ,  H05K2201/0723 ,  H05K2201/09227 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K2201/10674 ,  H05K2203/0207

    Abstract: Due to size and cost it becomes advantageous for integrated circuit (IC) manufacturers to use "single-ended" (one signal path per unique information path) high speed signals electrical contact pins (pins transmitting digital information that connect the integrated circuit to a printed circuit hoard) with a minimum number of surrounding powers and grounds. This lower cost method, however, creates electrical interference and coupling issues known as crosstalk between two adjacent signal paths in the via structure required to electrically connect the integrated circuit to the signal paths in the printed circuit hoard. Such crosstalk, in turn, increases jitter, degrades timing, and ultimately reduces the maximum operating speed, of the circuit (performance). This disclosure presents a structure using micro-plating, micro-drilling and micro-machining methods that isolates adjacent signals by placing a metal barrier that shunts coupling currents to ground. The micro-drilling methods also reduce the length of adjacent signal paths in a specific signal routing and controlled depth drilling sequence.

    Abstract translation: 由于尺寸和成本，集成电路（IC）制造商使用“单端”（每个唯一信息路径的一个信号路径）高速信号电接触引脚（引脚将数字信息连接到印刷电路 电路囤积）与最小数量的周围的权力和理由。 然而，这种较低成本的方法产生称为串联的电干扰和耦合问题，即将集成电路电连接到印刷电路板中的信号路径所需的通孔结构中的两个相邻信号路径之间的串扰。 这种串扰又增加了抖动，降低了定时，并最终降低了电路的最大工作速度（性能）。 本公开提供了使用微电镀，微钻孔和微加工方法的结构，其通过放置将耦合电流分流到地面的金属屏障来隔离相邻信号。 微钻孔方法还可以减小特定信号路由和受控深度钻井序列中相邻信号路径的长度。

    TUNED, INTERCHANGEABLE SHUTTLE BOARD RELAY
    49.
    发明申请
    TUNED, INTERCHANGEABLE SHUTTLE BOARD RELAY 审中-公开
    调谐，可互换的开关板继电器

    公开(公告)号：WO2015053933A1

    公开(公告)日：2015-04-16

    申请号：PCT/US2014/056881

    申请日：2014-09-23

    Applicant: R&D CIRCUITS, INC.

    IPC: H01H1/36 ,  H05K3/10 ,  H01H50/54

    CPC classification number: H01H1/403 ,  H01H1/0036 ,  H01H1/365 ,  H01H45/02

    Abstract: A shuttle board relay is provided that Is scalable to a specific pitch or routing density, the shuttle board relay provides a path with different sets of electrics! components that allows this via by allowing the integration of components and other types of customization. The shuttle board relay provides a minimally disruptive path to the signal. This minimizes loss and signal distortion, isolation and crosstalk am a function of pitch. Since pitch can be set, grounds included, etc, a design may be fully optimized for low cross talk.

    Abstract translation: 提供穿梭板继电器，可扩展到特定的间距或布线密度，梭式继电器提供不同套电气的路径！ 通过允许组件和其他类型的定制的集成来允许此通过的组件。 穿梭板继电器为信号提供了最小的破坏性路径。 这是减少损耗和信号失真，隔离和串扰是音高的函数。 由于音高可以设置，包括的理由等，一个设计可以完全优化低串扰。

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