公开(公告)号：KR1019960002072B1

公开(公告)日：1996-02-10

申请号：KR1019920019247

申请日：1992-10-20

Applicant: 삼성전자주식회사

Inventor： 남정림

IPC: H01L21/304

Abstract: forming a water-soluble polymer layer(23) on a semiconductor substrate(21); forming a photosensitive film(24) thereon; soft-baking the photosensitive film(24); exposing the photosensitive film(24) selectively to light; selectively forming an upper layer having resistance to a plasma by exposing the upper surface of the photosensitive film(24) to an organic metal substance; carrying out post exposure baking process of the photosensitive film having the selective upper layer; forming a photosensitive film pattern by removing the photosensitive film without the upper layer and the water-soluble polymer layer(23) in turn; and removing the photosensitive film pattern. Removal of the photosensitive film and its upper layer without demage of the substrate and other layers enhances reliability of the semiconductor device.

Abstract translation: 在半导体衬底（21）上形成水溶性聚合物层（23）; 在其上形成感光膜（24）; 软感光膜（24）; 将感光膜（24）选择性地曝光; 通过将感光膜（24）的上表面暴露于有机金属物质，选择性地形成对等离子体具有耐性的上层; 进行具有选择性上层的感光性膜的曝光后烘烤工序; 通过依次除去没有上层和水溶性聚合物层（23）的感光膜来形成感光膜图案; 并去除感光膜图案。 去除感光膜及其上层而不使衬底和其它层发生变形，这增强了半导体器件的可靠性。

公开(公告)号：KR100084717B1

公开(公告)日：1995-05-11

申请号：KR1019920002399

申请日：1992-02-18

Applicant: 삼성전자주식회사

Inventor： 박춘근 ,  남정림

IPC: G03F7/26

公开(公告)号：KR1019930017111A

公开(公告)日：1993-08-30

申请号：KR1019920000153

申请日：1992-01-08

Applicant: 삼성전자주식회사

Inventor： 남정림

IPC: H01L21/31

Abstract: 본 발명은 도포기의 회전부의 배기흐름을 조절하는 내측 보울을 설치하여 감광막의 두께를 균일하게 할 수 있는 감광제 도포장치를 제공하는데 있다.
이를 실현하기 위하여 본 발명은 웨이퍼를 회전시키는 회전기구와 외측 보울의 사이에, 배기시의 공기흐름을 조절하는 내측 보올을 승강가능하게 설치하여 웨이퍼 중앙부에서 주변부로 빠지는 공기를 억제함과 아울러 감광제의 리바운드를 막아 웨이퍼상에 형성되는 막질의 균일성을 높이고 감광제 디펙트를 방지토록 하고 있다.

公开(公告)号：KR1020090013905A

公开(公告)日：2009-02-06

申请号：KR1020070078044

申请日：2007-08-03

Applicant: 삼성전자주식회사

Inventor： 신상욱 ,  정병홍 ,  남정림 ,  박현 ,  강동조 ,  하재규 ,  장현석 ,  최호욱 ,  권태욱

IPC: H01L21/8242 ,  H01L27/108

Abstract: A method of manufacturing a semiconductor device is provided to suppress an undercut problem of the unit cell by forming the tungsten silicon film through physical vapor deposition process and improving a morphology of the tungsten silicon film. In a method of manufacturing a semiconductor device, a preliminary tunnel insulating film and the first conductive layer pattern are formed on the substrate(100). A dielectric layer and the second conductive film are successively formed on the first conductive layer pattern according to the surface profile of the first conductive layer pattern. The tungsten silicon film is formed on the second conductive film by the physical vapor deposition process. A control gate(126) includes a tungsten silicon film pattern(122) and a second conductive layer pattern(124), and a unit cell(134) includes the dielectric layer pattern(128), and the floating gate(130) and the preliminary insulating film(132) are formed by etching the tungsten silicon film, second conductive film, dielectric layer, first conductive layer pattern and preliminary tunnel insulating film.

Abstract translation: 提供一种制造半导体器件的方法，通过物理气相沉积工艺形成钨硅膜并改善钨硅膜的形态来抑制晶胞的底切问题。 在制造半导体器件的方法中，在衬底（100）上形成初步隧道绝缘膜和第一导电层图案。 根据第一导电层图案的表面轮廓，在第一导电层图案上依次形成电介质层和第二导电膜。 通过物理气相沉积工艺在第二导电膜上形成钨硅膜。 控制栅极（126）包括钨硅膜图案（122）和第二导电层图案（124），并且单元电池（134）包括电介质层图案（128）和浮动栅极（130）和 通过蚀刻钨硅膜，第二导电膜，电介质层，第一导电层图案和初步隧道绝缘膜来形成初步绝缘膜（132）。

公开(公告)号：KR100873894B1

公开(公告)日：2008-12-15

申请号：KR1020070065660

申请日：2007-06-29

Applicant: 삼성전자주식회사

Inventor： 김영후 ,  박현 ,  정병홍 ,  남정림

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L21/31051 ,  H01L27/2436

Abstract: The method of manufacturing the semiconductor device is provided to improve the performance characteristic and the reliability of the memory cell by forming easily the channel region in the first substrate irrespective of the high temperature heat treatment process. The method of manufacturing the semiconductor device comprises as follows. A step is for preparing the first substrate(100) and second substrate having a plurality of memory cells and selecting transistors. A step is for forming the first interlayer insulating film(140) and second inter metal dielectric(240) to cover a plurality of memory cells(120) and selecting transistors(130) on the first substrate and the second substrate. A step is for reducing the thickness of the second substrate by removing the lower surface site of the second substrate. A step is for welding the lower surface and the first interlayer insulating film of the second substrate having reduced thickness. A step is for forming the plugs connected with the selecting transistors on the first substrate and the second substrate.

Abstract translation: 提供制造半导体器件的方法是通过容易地形成第一衬底中的沟道区而改善存储单元的性能特性和可靠性，而与高温热处理工艺无关。 制造半导体器件的方法包括如下。 步骤是制备具有多个存储单元的第一衬底（100）和第二衬底以及选择晶体管。 步骤是用于形成第一层间绝缘膜（140）和第二金属间电介质（240）以覆盖多个存储单元（120）并在第一基板和第二基板上选择晶体管（130）。 步骤是通过去除第二基板的下表面部位来减小第二基板的厚度。 一个步骤是焊接具有减小的厚度的第二基板的下表面和第一层间绝缘膜。 步骤是用于形成与第一基板和第二基板上的选择晶体管连接的插头。

公开(公告)号：KR1020030084538A

公开(公告)日：2003-11-01

申请号：KR1020020034144

申请日：2002-06-18

Applicant: 삼성전자주식회사

Inventor： 여인준 ,  윤병문 ,  김경현 ,  조현호 ,  하상록 ,  남정림

IPC: H01L21/304

CPC classification number: H01L21/67051 ,  B08B3/02 ,  B08B3/12 ,  Y10S134/902 ,  Y10S438/906

Abstract: PURPOSE: A wafer cleaning system, a cleaning probe, and a wafer cleaning method are provided to be capable of reducing the generation of pattern damage while carrying out a wafer cleaning process. CONSTITUTION: A wafer cleaning system is provided with a cleaning vessel, a wafer support part(60) located in the cleaning vessel for supporting a cleaning process object wafer, a wafer rotating part(80) connected to the wafer support part(60) for rotating the wafer, a probe rotating part(50), and a probe vibrator for generating mega-sonic vibration. The wafer cleaning system further includes a cleaning probe(20), wherein the cleaning probe has a coupling end and an elongated end. At this time, the coupling end of the cleaning probe is connected to the probe rotating part(50) and the probe vibrator, and the elongated end of the cleaning probe is located near the wafer. At the time, the elongated end of the cleaning probe includes a curvilinear groove.

Abstract translation: 目的：提供晶片清洁系统，清洁探针和晶片清洁方法，以便在进行晶片清洁处理时能够减少图案损坏的产生。 构成：晶片清洗系统设置有清洁容器，位于清洁容器中的用于支撑清洁处理物体晶片的晶片支撑部分（60），连接到晶片支撑部分（60）的晶片旋转部分（80），用于 旋转晶片，探针旋转部分（50）和用于产生超音速振动的探针振动器。 晶片清洁系统还包括清洁探针（20），其中清洁探针具有联接端和细长端。 此时，清洁探针的联接端连接到探针旋转部分（50）和探针振动器，并且清洁探针的细长端位于晶片附近。 此时，清洁探头的细长端包括曲线槽。

公开(公告)号：KR1020030076898A

公开(公告)日：2003-09-29

申请号：KR1020020015906

申请日：2002-03-23

Applicant: 삼성전자주식회사

Inventor： 윤병문 ,  여인준 ,  하상록 ,  김경현 ,  조현호 ,  남정림

IPC: H01L21/304

CPC classification number: H01L21/67051 ,  B08B3/12 ,  Y10S134/902

Abstract: PURPOSE: A megasonic cleaning apparatus for manufacturing a semiconductor device is provided to be capable of preventing energy from being concentrated at the edge portion of a wafer. CONSTITUTION: A megasonic cleaning apparatus for manufacturing a semiconductor device is provided with a piezoelectric transducer(110) for generating megasonic energy and energy transmitting part(120) installed toward the radius direction against a semiconductor wafer for stirring a cleaning solution existing at the upper portion of the semiconductor wafer by using the energy generated from the piezoelectric transducer. At this time, the energy transmitting part is designed for removing particles of the semiconductor wafer by homogeneously flowing the stirred cleaning solution to the wafer radius direction using the energy generated from the piezoelectric transducer.

Abstract translation: 目的：提供一种用于制造半导体器件的兆声波清洗装置，以能够防止能量集中在晶片的边缘部分。 构成：用于制造半导体器件的兆声波清洗装置设置有压电换能器（110），该压电换能器用于产生兆声波能量和能量传递部分（120），该半导体能量和能量传递部分朝着半径方向安装在半导体晶片上，用于搅拌存在于上部的清洗液 通过使用从压电换能器产生的能量来实现。 此时，能量传递部被设计成通过使用从压电换能器产生的能量将搅拌的清洁溶液均匀地流动到晶片半径方向来去除半导体晶片的颗粒。

公开(公告)号：KR1020030015543A

公开(公告)日：2003-02-25

申请号：KR1020010049317

申请日：2001-08-16

Applicant: 삼성전자주식회사

Inventor： 이대엽 ,  남정림 ,  유도열 ,  이정우

IPC: H01L21/027

CPC classification number: G03F7/0392 ,  G03F1/50

Abstract: PURPOSE: Provided is a method for forming photoresist pattern, capable of controlling a residual film rate, which can provide a photolithography process obtaining a doping angle capable of forming a non-uniform channel by controlling the residual film rate of the photoresist pattern. CONSTITUTION: The method contains the steps of: forming a photoresist layer by spreading a photoresist for controlling the residual film rate, containing a compound represented by the formula 1 and a compound represented by the formula 2, on a semiconductor substrate, wherein the compound represented by the formula 1 has a molecular weight of 3000-30000g/mol and the compound represented by the formula 2 has a molecular weight of 1000-5000g/mol; exposing and developing the photoresist layer to form the residual film rate controlled photoresist pattern. The residual film rate of the photoresist pattern is 40-85%. In the formula, R is acetal or ter-butyloxy carbonyl(t-BOC), n and m are integers, n/(m+n) is 0.01-0.8, m/(m+n) is 1-£n/(m+n)|, and r is an integer of 8-40.

Abstract translation: 目的：提供一种能够控制残留膜速率的光致抗蚀剂图案的形成方法，其可以通过控制光致抗蚀剂图案的残留膜率来提供能够形成不均匀通道的掺杂角的光刻工艺。 方案：该方法包括以下步骤：在半导体衬底上形成光致抗蚀剂层，该光致抗蚀剂层通过将含有由式1表示的化合物和由式2表示的化合物控制残留膜速率的光致抗蚀剂铺展在其上， 式1的分子量为3000-30000g / mol，由式2表示的化合物的分子量为1000-5000g / mol; 曝光和显影光致抗蚀剂层以形成残留膜速度控制的光致抗蚀剂图案。 光致抗蚀剂图案的残留膜率为40-85％。 式中，R为缩醛或叔丁氧基羰基（t-BOC），n和m为整数，n /（m + n）为0.01-0.8，m /（m + n）为1〜 m + n）|，r为8〜40的整数。

公开(公告)号：KR1020020031492A

公开(公告)日：2002-05-02

申请号：KR1020000061987

申请日：2000-10-20

Applicant: 삼성전자주식회사

Inventor： 이석주 ,  양희홍 ,  남정림

IPC: H01L21/28

CPC classification number: H01L21/76807 ,  H01L21/76813

Abstract: PURPOSE: A method of forming a contact hole for a dual damascene line of a semiconductor device is provided to prevent an opening error of a contact hole due to reduced optical intensity. CONSTITUTION: An oxide layer is formed on a semiconductor substrate(500). A photoresist layer pattern is formed on the oxide layer. An oxide layer pattern having a groove(530) is formed by using the photoresist layer pattern as an etch mask. The photoresist layer pattern is removed. A photoresist layer pattern is formed on the oxide layer pattern. The photoresist layer pattern has an opening portion for exposing a bottom of the groove(530) of the oxide layer pattern. An oxide layer pattern(512) having a contact hole(550) is formed by using the photoresist layer pattern as an etch mask. The photoresist layer pattern is removed. A metal layer is filled into the contact hole(550) and the groove(530).

Abstract translation: 目的：提供一种形成半导体器件的双镶嵌线的接触孔的方法，以防止由于光强度降低导致的接触孔的开启误差。 构成：在半导体衬底（500）上形成氧化物层。 在氧化物层上形成光致抗蚀剂图案。 通过使用光致抗蚀剂层图案作为蚀刻掩模来形成具有凹槽（530）的氧化物层图案。 去除光致抗蚀剂层图案。 在氧化物层图案上形成光致抗蚀剂图案。 光致抗蚀剂层图案具有用于暴露氧化物层图案的凹槽（530）的底部的开口部分。 通过使用光致抗蚀剂层图案作为蚀刻掩模，形成具有接触孔（550）的氧化物层图案（512）。 去除光致抗蚀剂层图案。 金属层填充到接触孔（550）和凹槽（530）中。

公开(公告)号：KR100183731B1

公开(公告)日：1999-04-15

申请号：KR1019950027722

申请日：1995-08-30

Applicant: 삼성전자주식회사

Inventor： 조성목 ,  남정림

IPC: H01L21/66

Abstract: HMDS 처리 설비의 평가방법에 관하여 개시한다. 본 발명은 반도체 장치의 제조에 사용되는 HMDS처리 설비의 평가방법에 있어서, 반도체 웨이퍼 상에 네가티브형 감광막을 형성하는 단계와, 상기 감광막의 두께를 1차 측정하는 단계와, 상기 감광막이 형성된 웨이퍼를 전면노광하는 단계와, 상기 감광막이 형성된 웨이퍼를 베이크하는 단계와, 상기 베이크된 웨이퍼를 HMDS처리하여 감광막을 실릴레이션 반응시키는 단계와, 상기 실릴레이션 반응에 의하여 부피가 팽창된 감광막의 두께를 2차 측정하여 실릴레이션 반응전의 감광막의 두께와 비교함으로써 HMDS 처리 정도 및 균일도를 판단하는 단계를 포함하는 것을 특징으로 하는 HMDS처리 설비의 평가방법을 제공한다. 본 발명에 의한 HMDS 처리 설비의 평가 방법은 그 수행방법이 용이하고 정확하며 웨이퍼 표면 전면에 대한 균일도에 대한 정보도 얻을 수 있다.