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公开(公告)号：KR1020100111378A
公开(公告)日：2010-10-15
申请号：KR1020090029770
申请日：2009-04-07
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76897 , H01L21/02172 , H01L21/28525 , H01L21/32055 , H01L21/76877
Abstract: PURPOSE: The contact plug, and the semiconductor device including the same and manufacturing method thereof silver. CONSTITUTION: The contact plug, and the semiconductor device including the same and manufacturing method thereof silver. The first conductive film, and second conductive film is included. The first conductive film comprises poly-silicon it is formed on the sidewall of opening between the structure formed in the top of the substrate and the substrate(200).
Abstract translation: 目的：接触插头及包括其的半导体器件及其制造方法。 构成：接触插头和包括其的半导体器件及其制造方法。 包括第一导电膜和第二导电膜。 第一导电膜包括多晶硅，其形成在形成于基板顶部的结构与衬底（200）之间的开口侧壁上。
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公开(公告)号：KR1020070036466A
公开(公告)日：2007-04-03
申请号：KR1020050091502
申请日：2005-09-29
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L27/1128 , H01L21/76877 , H01L29/78654
Abstract: 박막 트랜지스터를 갖는 반도체소자 및 그 제조방법을 제공한다. 이 방법은 반도체 영역을 갖는 기판을 준비하는 것을 포함한다. 상기 기판 상에 절연막을 형성하되, 상기 절연막은 상기 반도체 영역을 노출시키는 콘택 홀을 갖도록 형성된다. 상기 절연막을 갖는 기판 상에 균일한 두께를 갖는 단결정 바디 패턴을 형성하되, 상기 바디 패턴의 일단은 상기 콘택 홀 상부를 덮으며 상기 콘택 홀을 채우도록 상기 바디 패턴의 일단으로부터 하부로 연장된 플러그를 갖도록 형성된다. 상기 단결정 바디 패턴의 측벽을 덮는 버퍼 스페이서를 형성한다. 상기 단결정 바디 패턴에 박막 트랜지스터를 형성한다.
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公开(公告)号：KR1020040062243A
公开(公告)日：2004-07-07
申请号：KR1020030000030
申请日：2003-01-02
Applicant: 삼성전자주식회사
IPC: H01L21/20
CPC classification number: H01L21/28194 , H01L29/513 , H01L29/517
Abstract: PURPOSE: A method for forming a compound layer of a semiconductor device, a capacitor using the same, and a method for forming a gate insulating layer are provided to change the temperature by controlling an interval between a stage and a substrate. CONSTITUTION: A stage including a lift pin(22) for supporting a substrate is prepared. The substrate(21) is supported by the lift pin of the stage(20). The first interval is formed between the stage and the substrate in order to maintain the temperature of the substrate at the first temperature by performing a temperature transmission process. The first layer is formed on the substrate under the process condition of the first temperature. The second interval is formed between the stage and the substrate in order to maintain the temperature of the substrate at the second temperature by performing the temperature transmission process.
Abstract translation: 目的：提供一种形成半导体器件的化合物层的方法，使用该化合物层的电容器和形成栅极绝缘层的方法，以通过控制载物台与基底之间的间隔来改变温度。 构成：准备包括用于支撑基板的升降销（22）的台架。 基板（21）由台（20）的升降销支撑。 通过进行温度传递处理，在载台和基板之间形成第一间隔，以便将基板的温度保持在第一温度。 第一层在第一温度的工艺条件下形成在衬底上。 通过进行温度传递过程，在载物台和基板之间形成第二间隔，以便将基板的温度保持在第二温度。
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公开(公告)号：KR1020140005422A
公开(公告)日：2014-01-15
申请号：KR1020120072472
申请日：2012-07-03
Applicant: 삼성전자주식회사
IPC: H01L27/146
CPC classification number: H01L31/02161 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14636 , H01L27/1464 , H01L27/14683 , H01L31/0203 , H01L31/18
Abstract: A semiconductor element forming method includes a step of preparing a first and second substrates, a step of forming metal wires on a first surface of the first substrate, a step of forming a filling insulating layer covering top surfaces of the metal wires and filling gaps between sides of the wires, a step of a buffer insualiating layer softer than the filling insulating layer on the filling insulating layer, a step of forming a capping insulating layer harder than the buffer insulating layer on the buffer insulating layer, and a step of bonding a surface of the second substrate and a surface of the capping insulating layer.
Abstract translation: 半导体元件形成方法包括制备第一和第二基板的步骤，在第一基板的第一表面上形成金属线的步骤，形成覆盖金属线的顶表面的填充绝缘层和填充间隙之间的间隙的步骤 电线的两侧，比填充绝缘层上的填充绝缘层柔软的缓冲层的步骤，在缓冲绝缘层上形成比缓冲绝缘层硬的加盖绝缘层的工序，以及将 第二基板的表面和封盖绝缘层的表面。
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公开(公告)号：KR101286239B1
公开(公告)日：2013-07-15
申请号：KR1020070085455
申请日：2007-08-24
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/7685 , H01L21/76805 , H01L21/76814 , H01L21/76888 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , Y10T428/31678 , H01L2924/00
Abstract: 산소 포획 패턴을 갖는 반도체 소자의 배선 구조 및 그 제조 방법이 제공된다. 상기 반도체 소자의 배선 구조는 반도체 기판 상에 형성된 하부 층간절연막을 구비한다. 상기 하부 층간절연막 상에 차례로 적층되는 배치되는 금속막 패턴과 캐핑막 패턴이 제공된다. 상기 캐핑막 패턴 상에 배치되며, 도전성 산소 포획(trap) 패턴을 구비하는 산소 포획 패턴이 제공된다. 아울러, 상기 반도체 소자의 배선 구조의 제조 방법도 제공된다.
금속 배선, 산소 포획, 콘택 저항-
Patent Agency Ranking
公开(公告)号：KR1020020068900A
公开(公告)日：2002-08-28
申请号：KR1020010009280
申请日：2001-02-23
Applicant: 삼성전자주식회사
Inventor： 강동조
IPC: H01L21/28
Abstract: PURPOSE: A semiconductor device having a borderless contact plug and a method for fabricating the same are provided to prevent leakage of current generating from a boundary face between a borderless contact plug and a semiconductor substrate though an STI layer is overetched. CONSTITUTION: A trench(t) is formed in a semiconductor substrate(200). A sidewall oxide layer(210) and a liner are formed on an inner wall of the trench(t). An oxide layer is deposited on the semiconductor substrate(200). An STI layer(220) is formed by polishing the semiconductor substrate(200). A gate electrode and an active region(230) are formed on the semiconductor substrate(200). An etch stopper(240) and an interlayer dielectric(250) are formed thereon. A contact hole is formed by etching the interlayer dielectric(250) and the etch stopper(240). An insulating material is formed on the whole surface of the semiconductor substrate(200). An insulating layer(275) is formed on an inner wall of the contact hole and an inner wall of a recess. A borderless contact hole(280) is formed by burying the contact hole and the recess with a conductive material.
Abstract translation: 目的：提供一种具有无边界接触插塞的半导体器件及其制造方法，以防止通过STI层被过蚀刻从无边界接触插塞和半导体衬底之间的边界面产生的电流泄漏。 构成：在半导体衬底（200）中形成沟槽（t）。 在沟槽（t）的内壁上形成侧壁氧化物层（210）和衬垫。 氧化物层沉积在半导体衬底（200）上。 通过研磨半导体衬底（200）形成STI层（220）。 在半导体衬底（200）上形成栅电极和有源区（230）。 在其上形成蚀刻停止器（240）和层间电介质（250）。 通过蚀刻层间电介质（250）和蚀刻停止层（240）形成接触孔。 绝缘材料形成在半导体衬底（200）的整个表面上。 绝缘层（275）形成在接触孔的内壁和凹部的内壁上。 通过用导电材料掩埋接触孔和凹部来形成无边界接触孔（280）。
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公开(公告)号：KR1020080078972A
公开(公告)日：2008-08-29
申请号：KR1020070018886
申请日：2007-02-26
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/143 , H01L45/144
Abstract: A method of manufacturing a phase change memory device is provided to reduce the size of the phase change memory device by reducing active sheet resistance. A method of manufacturing a phase change memory device includes the steps of: forming an insulation layer pattern(300) with an opening on a semiconductor substrate(200); forming a buried structure(310) in which a first impurity is doped to have a height different than that of an inlet of the opening while filling the opening; forming a spacer(330) of metal in a contact region between the buried structure and the insulation layer pattern; forming a diode(610) composed of a second impurity on the buried structure by a selective epitaxial growth; forming a first electrode(640) on the diode to be electrically connected to the diode; forming a phase change material layer pattern(670) on the first electrode; and forming a second electrode(680) on the phase change material layer pattern.
Abstract translation: 提供一种制造相变存储器件的方法，通过减小活性薄片电阻来减小相变存储器件的尺寸。 制造相变存储器件的方法包括以下步骤：在半导体衬底（200）上形成具有开口的绝缘层图案（300）; 形成掩埋结构（310），其中掺杂第一杂质的高度不同于填充开口的开口的入口的高度; 在所述掩埋结构和所述绝缘层图案之间的接触区域中形成金属间隔物（330）; 通过选择性外延生长在掩埋结构上形成由第二杂质构成的二极管（610）; 在二极管上形成电连接到二极管的第一电极（640）; 在所述第一电极上形成相变材料层图案（670）; 以及在所述相变材料层图案上形成第二电极（680）。
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公开(公告)号：KR100715267B1
公开(公告)日：2007-05-08
申请号：KR1020050049387
申请日：2005-06-09
Applicant: 삼성전자주식회사
IPC: H01L27/11
CPC classification number: H01L21/76855 , H01L21/28518 , H01L21/76843 , H01L21/76895 , H01L21/76898 , H01L21/8221 , H01L27/0688
Abstract: 단위 소자들이 수직으로 배치되는 스택형 반도체 장치 및 그 제조 방법에서, 상기 스택형 반도체 장치는, 기판과, 상기 기판 상에 형성되고, 내부에 실리콘막 패턴을 포함하고, 상기 실리콘막 패턴과 상기 기판을 부분적으로 노출하는 콘택홀을 갖는 박막 구조물과, 상기 노출된 실리콘막 패턴을 덮고 제1 물질로 이루어지는 제1 오믹 구조물과, 상기 노출된 기판을 덮고 상기 제1 물질과 다른 제2 물질을 포함하는 제2 오믹 구조물 및 상기 콘택홀 내부를 채우는 금속 패턴을 포함한다. 상기한 스택형 반도체 장치는 실리콘막 패턴 및 기판을 덮는 서로 다른 오믹 구조물을 가짐으로서 상기 실리콘막 패턴 및 기판의 접촉 저항을 감소시킬 수 있다.
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公开(公告)号：KR1020060118078A
公开(公告)日：2006-11-23
申请号：KR1020050040538
申请日：2005-05-16
Applicant: 삼성전자주식회사
CPC classification number: H01L21/76897 , H01L21/76859 , H01L21/76889 , H01L27/1104
Abstract: A method for manufacturing a stack type semiconductor device is provided to restrain the erosion of a single crystal silicon pattern by forming uniformly a metal silicide layer using a nitrogen doped region. A first interlayer dielectric(102a), a single crystal silicon pattern(108a) and a second interlayer dielectric(110a) are sequentially formed on a single crystal silicon substrate(100). The single crystal silicon layer is used as an upper active region. A contact hole for exposing an upper portion of the single crystal silicon substrate and sidewalls of the single crystal silicon pattern to the outside is formed on the resultant structure by etching. A nitrogen doped region(118) is formed at the exposed sidewalls of the single crystal silicon pattern by using a nitrogen ion implantation. A barrier metal is formed along an upper surface of the resultant structure. A heat treatment is performed on the resultant structure to form a lower metal silicide layer on the exposed single crystal silicon substrate and a side silicide layer on the sidewalls of the single crystal silicon pattern.
Abstract translation: 提供一种堆叠型半导体器件的制造方法，通过使用氮掺杂区域均匀地形成金属硅化物层来抑制单晶硅图案的侵蚀。 在单晶硅衬底（100）上依次形成第一层间电介质（102a），单晶硅图案（108a）和第二层间电介质（110a）。 单晶硅层用作上活性区。 通过蚀刻在所得结构上形成用于将单晶硅衬底的上部和单晶硅图案的侧壁暴露于外部的接触孔。 通过使用氮离子注入在单晶硅图案的暴露的侧壁处形成氮掺杂区域（118）。 沿所得结构的上表面形成阻挡金属。 对所得结构进行热处理，以在暴露的单晶硅衬底上形成下金属硅化物层，并在单晶硅图案的侧壁上形成侧硅化物层。
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公开(公告)号：KR1020090013905A
公开(公告)日：2009-02-06
申请号：KR1020070078044
申请日：2007-08-03
Applicant: 삼성전자주식회사
IPC: H01L21/8242 , H01L27/108
Abstract: A method of manufacturing a semiconductor device is provided to suppress an undercut problem of the unit cell by forming the tungsten silicon film through physical vapor deposition process and improving a morphology of the tungsten silicon film. In a method of manufacturing a semiconductor device, a preliminary tunnel insulating film and the first conductive layer pattern are formed on the substrate(100). A dielectric layer and the second conductive film are successively formed on the first conductive layer pattern according to the surface profile of the first conductive layer pattern. The tungsten silicon film is formed on the second conductive film by the physical vapor deposition process. A control gate(126) includes a tungsten silicon film pattern(122) and a second conductive layer pattern(124), and a unit cell(134) includes the dielectric layer pattern(128), and the floating gate(130) and the preliminary insulating film(132) are formed by etching the tungsten silicon film, second conductive film, dielectric layer, first conductive layer pattern and preliminary tunnel insulating film.
Abstract translation: 提供一种制造半导体器件的方法，通过物理气相沉积工艺形成钨硅膜并改善钨硅膜的形态来抑制晶胞的底切问题。 在制造半导体器件的方法中，在衬底（100）上形成初步隧道绝缘膜和第一导电层图案。 根据第一导电层图案的表面轮廓，在第一导电层图案上依次形成电介质层和第二导电膜。 通过物理气相沉积工艺在第二导电膜上形成钨硅膜。 控制栅极（126）包括钨硅膜图案（122）和第二导电层图案（124），并且单元电池（134）包括电介质层图案（128）和浮动栅极（130）和 通过蚀刻钨硅膜，第二导电膜，电介质层，第一导电层图案和初步隧道绝缘膜来形成初步绝缘膜（132）。
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