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    강유전체 박막의 형성 방법 및 이를 이용한 반도체 장치의제조 방법
    41.
    发明公开
    강유전체 박막의 형성 방법 및 이를 이용한 반도체 장치의제조 방법 有权
    形成电介质层的方法和使用其制造半导体器件的方法

    公开(公告)号：KR1020100009013A

    公开(公告)日：2010-01-27

    申请号：KR1020080069681

    申请日：2008-07-17

    Applicant: 삼성전자주식회사

    Inventor： 최석헌 ,  이종원 ,  홍창기 ,  윤보언

    IPC: H01L21/31 ,  H01L27/105

    CPC classification number: H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

    Abstract: PURPOSE: A method for forming a ferroelectric thin film and a semiconductor device manufacturing method using the same are provided to flatten only rough portion of the ferroelectric thin film while suppressing the abrasion of bulk portion of the ferroelectric thin film by using slurry composition. CONSTITUTION: A conductive structure is formed on a substrate(S110). A pre ferroelectric film is formed on the conductive structure(S120). The surface of the pre ferroelectric film is chemically-mechanically polished using slurry composition(S130). A ferroelectric film with improved surface roughness is washed(S140). The ferroelectric film is heat-treated to cure the damage of the film surface(S150).

    Abstract translation: 目的：提供一种形成铁电薄膜的方法及使用该方法的半导体器件制造方法，通过使用浆料组合物来抑制铁电薄膜的本体部分的磨损，使粗铁电薄膜的平坦化。 构成：在基板上形成导电结构（S110）。 在导电结构上形成预铁电体膜（S120）。 使用浆料组合物对预铁电体膜的表面进行化学机械抛光（S130）。 洗涤具有改善的表面粗糙度的铁电体膜（S140）。 对铁电体膜进行热处理以固化膜表面的损伤（S150）。

    반도체 메모리 소자 및 그 제조 방법
    42.
    发明授权
    반도체 메모리 소자 및 그 제조 방법 失效
    半导体存储器件及其制造方法

    公开(公告)号：KR100881181B1

    公开(公告)日：2009-02-05

    申请号：KR1020060111879

    申请日：2006-11-13

    Applicant: 삼성전자주식회사

    Inventor： 최석헌 ,  백인규 ,  이준영 ,  김중현 ,  홍창기 ,  손윤호

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L28/20 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

    Abstract: A semiconductor memory device includes a first conductive line on a semiconductor substrate, an interlayer insulating layer on the first conductive line, a second conductive line on the interlayer insulating layer, and a memory cell in an hole through the interlayer insulating layer wherein the first and second conductive lines cross, the memory cell including a discrete resistive memory material region disposed in the hole and electrically connected between the first and second conductive lines. The resistive memory material region may be substantially contained within the hole. In some embodiments, contact between the resistive memory material region and the interlayer insulating layer is substantially limited to sidewalls of the interlayer insulating layer in the hole.

    테이퍼진 패턴들을 갖는 반도체 장치의 제조방법
    43.
    发明公开
    테이퍼진 패턴들을 갖는 반도체 장치의 제조방법 无效
    具有锥形图案的半导体装置的制造方法

    公开(公告)号：KR1020090003767A

    公开(公告)日：2009-01-12

    申请号：KR1020070066700

    申请日：2007-07-03

    Applicant: 삼성전자주식회사

    Inventor： 최석헌 ,  홍창기 ,  윤보언 ,  고영호 ,  유동철 ,  임종흔

    IPC: G01R1/067

    CPC classification number: G01R1/067 ,  H01L21/02 ,  H01L21/302 ,  H01L21/78

    Abstract: A method for manufacturing a semiconductor device with tapered patterns is provided to form columnar patterns on a surface of a donor wafer by using a bonding process and a cleaving process. An acceptor wafer and a donor wafer(200') are prepared. The acceptor wafer includes a first pattern and a second pattern made of the material different from the first pattern. The donor wafer includes the hydrogen ion implantation region. The respective first and second bonding areas are formed in the hydrogen ion implantation region of the donor wafer corresponding to the first and second patterns of the acceptor wafer by bonding the accepter wafer and the donor wafer. The bonding strength of the first bonding area is greater than the second bonding area. The first bonding area is separated from the donor wafer by separating the acceptor wafer and the donor wafer. The second bonding area is exposed while being adhered to the donor wafer and is protruded from the donor wafer. The exposed second bonding area is etched and the tapered pattern is formed in the donor wafer.

    Abstract translation: 提供了一种用于制造具有锥形图案的半导体器件的方法，以通过使用接合工艺和切割工艺在施主晶片的表面上形成柱状图案。 制备受体晶片和施主晶片（200'）。 受主晶片包括由不同于第一图案的材料制成的第一图案和第二图案。 施主晶片包括氢离子注入区域。 相应的第一和第二接合区域通过接合接收晶片和施主晶片而形成在施主晶片的氢离子注入区域中，其对应于受主晶片的第一和第二图案。 第一接合区域的接合强度大于第二接合面积。 通过分离受体晶片和施主晶片，将第一结合区域与施主晶片分离。 第二接合区域在被粘附到施主晶片的同时被暴露并且从施主晶片突出。 蚀刻暴露的第二接合区域，并且在施主晶片中形成锥形图案。

    스택형 반도체 소자에서 단결정 실리콘 패턴 형성 방법.
    44.
    发明授权
    스택형 반도체 소자에서 단결정 실리콘 패턴 형성 방법. 有权
    在堆叠半导体器件中形成单晶硅图案的方法

    公开(公告)号：KR100840785B1

    公开(公告)日：2008-06-23

    申请号：KR1020070016427

    申请日：2007-02-16

    Applicant: 삼성전자주식회사

    Inventor： 임종흔 ,  홍창기 ,  윤보언 ,  배대록 ,  윤성규 ,  최석헌

    IPC: H01L21/31

    CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/8221

    Abstract: A method for forming a single crystal silicon pattern in a stacked semiconductor device is provided to simplify a pattern forming process by forming the single crystal silicon pattern without using a photolithography process. A hydrogen ion is implanted on an upper surface of a first substrate(100), which is made of a single crystal silicon, such that a hydrogen ion implantation region(102) is formed at a portion displaced from the upper surface of the first substrate. A silicon oxide film pattern is formed to cover the second substrate on a second substrate, which is made of a single crystal signal. An upper surface of the silicon oxide film pattern is partially protruded. The upper surface of the silicon oxide film pattern, which is formed on the second substrate, is bonded with the upper surface of the first substrate. A portion of the first substrate is separated from the second substrate by using the hydrogen ion implantation region as a cutting surface. A single crystal silicon pattern is selectively formed on the silicon oxide pattern.

    Abstract translation: 提供了一种用于在层叠半导体器件中形成单晶硅图案的方法，以通过在不使用光刻工艺的情况下形成单晶硅图案来简化图案形成处理。 在由单晶硅制成的第一衬底（100）的上表面上注入氢离子，使得在从第一衬底的上表面偏移的部分形成氢离子注入区（102） 。 在由单晶信号制成的第二基板上形成氧化硅膜图形以覆盖第二基板。 氧化硅膜图案的上表面部分地突出。 形成在第二基板上的氧化硅膜图案的上表面与第一基板的上表面接合。 通过使用氢离子注入区域作为切割表面，第一衬底的一部分与第二衬底分离。 在氧化硅图案上选择性地形成单晶硅图案。

    반도체 장치의 형성 방법
    45.
    发明授权
    반도체 장치의 형성 방법 失效
    形成半导体器件的方法

    公开(公告)号：KR100806351B1

    公开(公告)日：2008-02-27

    申请号：KR1020070016450

    申请日：2007-02-16

    Applicant: 삼성전자주식회사

    Inventor： 임종흔 ,  홍창기 ,  윤보언 ,  윤성규 ,  최석헌 ,  한상엽

    IPC: H01L21/76

    CPC classification number: H01L21/76229 ,  H01L21/3212

    Abstract: A method for fabricating a semiconductor device is provided to minimize a dishing phenomenon at a planarization process for a crystalline semiconductor layer formed in a peripheral region and/or a test device group region. A pattern having trenches(203a,203b) is formed on a semiconductor substrate(200) to expose the substrate, and then a semiconductor layer is formed to bury the trenches. The semiconductor layer is primarily planarized when the pattern is not exposed. A crystalline semiconductor layer is formed on the primarily planarized semiconductor layer by performing an epitaxial growth process. The crystalline semiconductor layer is secondarily planarized to form a crystalline semiconductor pattern. The substrate has a first region and a second region wider than the first region.

    Abstract translation: 提供了一种用于制造半导体器件的方法，以便在形成在周边区域和/或测试器件组区域中的结晶半导体层的平坦化处理期间最小化凹陷现象。 在半导体衬底（200）上形成具有沟槽（203a，203b）以露出衬底的图案，然后形成半导体层以埋设沟槽。 当图案不暴露时，半导体层主要是平面化的。 通过进行外延生长工艺，在主要平坦化的半导体层上形成晶体半导体层。 晶体半导体层被二次平坦化以形成晶体半导体图案。 衬底具有比第一区域宽的第一区域和第二区域。

    강유전체 박막의 제조 방법 및 이를 이용한 반도체 장치의제조 방법
    46.
    发明公开
    강유전체 박막의 제조 방법 및 이를 이용한 반도체 장치의제조 방법 失效
    形成电介质层的方法和使用其制造半导体器件的方法

    公开(公告)号：KR1020060119042A

    公开(公告)日：2006-11-24

    申请号：KR1020050041568

    申请日：2005-05-18

    Applicant: 삼성전자주식회사

    Inventor： 최석헌 ,  배병재 ,  손윤호 ,  홍창기 ,  박정헌

    IPC: H01L27/105 ,  H01L21/304

    CPC classification number: H01L27/11507 ,  G11C11/22 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/75

    Abstract: A method for fabricating a ferroelectric layer and a method for manufacturing a semiconductor device using the same are provided to realize a thin ferroelectric layer and to improve degradation thereof by employing a CMP process for polishing a surface of a preliminary ferroelectric layer. A preliminary ferroelectric layer is formed on a substrate(100). The preliminary ferroelectric layer has a thickness of 500 to 1500Š. The preliminary ferroelectric layer is selected from a group consisting of PZT[Pb(Zr,Ti)O3], SBT(SrBi2Ta2O9), BLT[Bi(La,Ti)O3], PLZT[Pb(La,Zr)TiO3], and BST[Bi(Sr,Ti)O 3]. A surface of the preliminary ferroelectric layer is polished to form a ferroelectric layer(115) on the substrate. The ferroelectric layer is cured. The ferroelectric layer has a thickness of 200 to 1000 Š.

    Abstract translation: 提供一种制造铁电体层的方法以及使用该方法制造半导体器件的方法，以实现薄铁电体层并通过采用用于抛光预备铁电层的表面的CMP工艺来改善其劣化。 在基板（100）上形成初步铁电层。 初步铁电层的厚度为500〜1500μs。 初步铁电层选自PZT [Pb（Zr，Ti）O3]，SBT（SrBi2Ta2O9），BLT [Bi（La，Ti）O3]，PLZT [Pb（La，Zr）TiO3]和 BST [Bi（Sr，Ti）O 3]。 对初级强电介质层的表面进行研磨，在基板上形成铁电体层（115）。 铁电层被固化。 铁电层的厚度为200〜1000Š。

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