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公开(公告)号：KR1020150108992A
公开(公告)日：2015-10-01
申请号：KR1020140031720
申请日：2014-03-18
Applicant: 한국전자통신연구원
CPC classification number: H03K17/122 , H02M3/1588 , H02M2001/0009 , H02M2001/0048 , H03K2217/0036 , Y02B70/1466 , Y02B70/1491
Abstract: 발전소자용 DC-DC 승압형변환기는양단전압및 전원전류를발생시키는발전소자, 제1 노드와제2 노드사이에연결되고, 전원전류에의해충전되는인덕터, 제2 노드와제3 노드사이에연결되는제1 복수의트랜지스터들을포함하는제1 스위치부, 제2 노드와접지단자에연결되는제2 복수의트랜지스터들을포함하는제2 스위치부, 양단전압을감지하여, 발전소자로부터출력되는입력전압이양단전압과소정의비율로유지되도록제어신호를제1 및제2 스위치부에출력하는최대전력추종제어부, 발전소자및 상기인덕터사이에연결되며, 상기전원전류의크기에따른상기제1 및제2 스위치부의활성화되는상기제1 및제2 복수의트랜지스터의개수를제어하는신호를출력하는전류감지부, 및신호를통해제1 및제2 스위치부의제1 및제2 복수의트랜지스터들을연결하는스위치선택부를포함한다.
Abstract translation: 用于发电装置的DC-DC升压转换器包括产生电力电流的电力产生装置和其两端之间的电压，连接在第一节点和第二节点之间并且被充电的电力的电感器， 第一开关单元，包括连接在第二节点和第三节点之间的多个第一晶体管，第二开关单元，其包括连接到第二节点的多个第二晶体管和接地端子，最大功率点 跟踪控制单元，其感测其两端之间的电压，并且向第一和第二开关单元输出控制信号，以将其从发电设备输出的输入电压与其两端之间的电压设定为预设比;电流感测单元 其连接在发电装置和电感器之间，并且输出用于控制第一和第二转子的数量的信号 根据功率电流的振幅激活的第一和第二开关单元的开关，以及通过该信号连接第一和第二开关单元的第一和第二晶体管的开关选择单元。
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公开(公告)号：KR1020130071782A
公开(公告)日：2013-07-01
申请号：KR1020110139202
申请日：2011-12-21
Applicant: 한국전자통신연구원
CPC classification number: G06F13/4059 , G06F13/1605 , G06F13/1668 , G06F13/4031 , Y02D10/14
Abstract: PURPOSE: A bus bridge apparatus is provided to maximize data transmission performance among interconnections, by transmitting and receiving data by considering characteristics among different interconnections. CONSTITUTION: A slave port (210) performs interface with a master device of a bus based interconnection (110), and receives read and write transmission command, address data and write data from the master device, and transmits read data to the master device. A command controller (220) receives the transmission command, and an address buffer (230) stores the address data. A write data buffer (240) stores the write data, and a read data buffer (270) stores the read data. A protocol converter (260) outputs the write data of the master device to the slave device, by using the address and write data in case of the write transmission command. [Reference numerals] (200) Bus bridge apparatus; (210) Slave port; (220) Bus based interconnection; (230) Address buffer; (240) Write data buffer; (250) Transmission mode controller; (260) Protocol converter; (270) Read data buffer; (AA) Bus based interconnection; (BB) Network based interconnection
Abstract translation: 目的：提供一种总线桥接装置，通过考虑不同互连之间的特性，通过发送和接收数据来最大化互连之间的数据传输性能。 构成：从端口（210）与基于总线的互连（110）的主设备进行接口，并且从主设备接收读写传输命令，地址数据和写数据，并将读数据发送到主设备。 命令控制器（220）接收发送命令，地址缓冲器（230）存储地址数据。 写数据缓冲器（240）存储写数据，读数据缓冲器（270）存储读数据。 在写入发送命令的情况下，协议转换器（260）通过使用地址和写入数据将主设备的写入数据输出到从设备。 （附图标记）（200）总线桥装置; （210）从站端口; （220）总线互连; （230）地址缓冲区; （240）写入数据缓冲区; （250）传输模式控制器; （260）协议转换器; （270）读数据缓冲; （AA）总线互连; （BB）基于网络的互连
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公开(公告)号：KR1020130058286A
公开(公告)日：2013-06-04
申请号：KR1020110124209
申请日：2011-11-25
Applicant: 한국전자통신연구원 , 고려대학교 산학협력단
IPC: G06T7/00
CPC classification number: G06K9/00369 , G06K9/6269
Abstract: PURPOSE: A pedestrian detection method of a pedestrian detection device is provided to perform pedestrian detection on a search window using a second classifier with high accuracy after reducing the number of search windows, thereby performing highly accurate detection of an object while reducing the complexity of detection procedure and power consumption. CONSTITUTION: A pedestrian detection device obtains an image from a digital image device and performs blocking of search windows(210,220). The pedestrian detection device selects a specific block from blocks determined by a pre-learned classifier(230) and produces a specific vector of HOG features from the selected block(240,250). The pedestrian detection device calculates a SVM(Support Vector Machine) response value using the produced feature vector, and performs a first object detection by applying the response value to an AdaBoost Classifier(260,270). If a pedestrian is detected at the first object detection, the pedestrian detection device performs a second object detection to the search window(280). [Reference numerals] (210) Obtain an image; (220) Performs blocking of search windows; (230) Pre-learned classifier; (240) Select a specific block; (250) Produce a specific vector; (260) Calculates a SVM response value; (270) Perform a first object detection; (280) Perform a second object detection; (290) Output decision; (AA) No; (BB) Yes
Abstract translation: 目的：提供一种行人检测装置的行人检测方法，在减少搜索窗口数量之后，使用第二分类器在搜索窗口上进行行人检测，从而对目标进行高精度的检测，同时降低检测的复杂度 程序和功耗。 规定：行人检测装置从数字图像装置获取图像并执行搜索窗口的封锁（210,220）。 行人检测装置从预先学习的分类器（230）确定的块中选择特定的块，并从所选择的块（240,250）生成特定的HOG特征向量。 行人检测装置使用所产生的特征向量来计算SVM（Support Vector Machine）响应值，并通过将响应值应用于AdaBoost分类器（260,270）来执行第一对象检测。 如果在第一物体检测中检测到行人，则行人检测装置对搜索窗口进行第二物体检测（280）。 （附图标记）（210）获取图像; （220）执行搜索窗口的阻止; （230）预先学习分类器; （240）选择一个特定块; （250）生成特定载体; （260）计算SVM响应值; （270）执行第一个对象检测; （280）执行第二对象检测; （290）产出决定; （AA）否 （BB）是的
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公开(公告)号：KR101228017B1
公开(公告)日：2013-02-01
申请号：KR1020090121888
申请日：2009-12-09
Applicant: 한국전자통신연구원
CPC classification number: G06K9/00664 , G06K9/00791 , G06K9/6807
Abstract: 본 발명은 영상 인식 장치 및 방법에 관한 것으로, 본 발명의 일 실시 예에 따른 위치 정보 기반 영상 인식 장치는, 현재 위치 정보를 수신하는 GPS 수신부; 주변 영상을 촬영하여 주변 영상 데이터를 취득하는 주변 영상 정보 취득부; 각각의 영상 인식 대상에 대한 영상 인식 학습 정보를 저장하는 영상 인식 학습 정보 데이터 베이스; 상기 수신된 현재 위치 정보를 기반으로 현재 위치의 지리적 특성에 연관된 영상 인식 학습 정보를 상기 영상 인식 학습 정보 데이터 베이스로부터 선택하는 영상 인식 학습 정보 선택부; 및 상기 선택된 영상 인식 학습 정보에 기반하여 상기 취득된 주변 영상 데이터의 영상 인식을 수행하는 영상 인식 처리부를 포함한다.
상술한 바와 같은 본 발명은, 현재 위치의 지리적 특성에서 나타날 수 있는 대상에 대한 영상 인식 학습 정보만을 추출하여, 이를 주변 영상 정보와 비교함으로써 영상 인식 처리에 소모되는 연산량을 줄일 수 있는 이점이 있다.
영상 인식, 위치 정보, 지리적 특성-
Patent Agency Ranking
公开(公告)号：KR1020110073173A
公开(公告)日：2011-06-29
申请号：KR1020100028448
申请日：2010-03-30
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A memory system comprising a plurality of DMA channels and an integrating management method for a plurality of DMA channels are provided to improve data transmission efficiency of a memory controller by the integrated management of multichannel memory controller and connected multiple DMA channels. CONSTITUTION: A memory controller(200) performs data transceiving operation with a memory(100). The memory controller comprises multiple channels which are physically separated each other. A DMA controller (300) is connected to the multiple channels of the memory controller and includes multiple DMA channels which are physically separated each other. The DMA controller performs data transceiving operation with the memory through the multiple DMA channels and the memory controller. An access module(400) connects the channels of the memory controller with the DMA channels each other.
Abstract translation: 目的：提供包括多个DMA通道的存储系统和用于多个DMA通道的集成管理方法，以通过多通道存储器控制器和连接的多个DMA通道的集成管理来提高存储器控制器的数据传输效率。 构成：存储器控制器（200）用存储器（100）执行数据收发操作。 存储器控制器包括物理上彼此分离的多个通道。 DMA控制器（300）连接到存储器控制器的多个通道，并且包括物理上彼此分离的多个DMA通道。 DMA控制器通过多个DMA通道和存储器控制器与存储器执行数据收发操作。 访问模块（400）将存储器控制器的通道与DMA通道相互连接。
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公开(公告)号：KR1020110011533A
公开(公告)日：2011-02-08
申请号：KR1020100056982
申请日：2010-06-16
Applicant: 한국전자통신연구원
Abstract: PURPOSE: An absolute difference operation device is provided to use one adder and one comparator, thereby performing absolute difference operation with a low logic surface load. CONSTITUTION: A comparator(410) compares the size between two integers. According to the comparing result, the first and the second selectors(420,430) respectively select/output one among two integers. An inverter(440) mending-process a selection result value of the second selector. An adder(450) adds 1 and a value which is mending-processes by the inverter and the selection result value of the first selector.
Abstract translation: 目的：提供绝对差分运算器件，使用一个加法器和一个比较器，从而在低逻辑表面负载下执行绝对差运算。 构成：比较器（410）比较两个整数之间的大小。 根据比较结果，第一和第二选择器（420,430）分别选择/输出两个整数之一。 逆变器（440）对第二选择器的选择结果值进行修补处理。 加法器（450）将反相器进行修补处理的值和第一选择器的选择结果值相加1。
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公开(公告)号：KR1020110011528A
公开(公告)日：2011-02-08
申请号：KR1020100052154
申请日：2010-06-03
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A DMA controller with an interrupt control processor is provided to reduce interrupt control load of a main processors. CONSTITUTION: A DMA(Direct Memory Access) channel register bank(240) stores a DMA channel operation request and a DMA set point. An interrupt control processor(250) performs a control program stored in a program memory(220). A DMA channel control module(270) controls operation of a DMA channel(150) according to the DMA set value by responding to a DMA channel activation command. An interrupt/DMA request and cancel module(260) generates a release signal about an interrupt processed by the interrupt control processor.
Abstract translation: 目的：提供具有中断控制处理器的DMA控制器，以减少主处理器的中断控制负载。 构成：DMA（直接存储器访问）通道寄存器组（240）存储DMA通道操作请求和DMA设定点。 中断控制处理器（250）执行存储在程序存储器（220）中的控制程序。 DMA通道控制模块（270）通过响应DMA通道激活命令，根据DMA设定值来控制DMA通道（150）的操作。 中断/ DMA请求和取消模块（260）产生关于由中断控制处理器处理的中断的释放信号。
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公开(公告)号：KR1020100072699A
公开(公告)日：2010-07-01
申请号：KR1020080131186
申请日：2008-12-22
Applicant: 한국전자통신연구원
CPC classification number: G06F13/122
Abstract: PURPOSE: A multi channel data transfer device is provided to minimize repetitiveness of register setting according to a multi channel transfer, thereby reducing a control load by a processor. CONSTITUTION: A plurality of channel controllers(327_1~327_n) are respectively connected to a plurality of peripheral devices(331~33n). A plurality of control registers(326_1~326_n) stores setting data for controlling operation of each channel control device. A common register control unit(324) transfers a common setting data to whole or a part of the plurality of control register. The common setting data is commonly applied to whole or a part of the plurality of channel control device.
Abstract translation: 目的：提供多通道数据传输装置，以根据多通道传输最小化寄存器设置的重复性，从而减少处理器的控制负载。 构成：多个通道控制器（327_1〜327_n）分别连接到多个外围设备（331〜33n）。 多个控制寄存器（326_1〜326_n）存储用于控制各通道控制装置的动作的设定数据。 公共寄存器控制单元（324）将公共设置数据传送到多个控制寄存器的全部或一部分。 通常的设定数据通常应用于多个通道控制装置的全部或一部分。
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公开(公告)号：KR1020100070821A
公开(公告)日：2010-06-28
申请号：KR1020080129544
申请日：2008-12-18
Applicant: 한국전자통신연구원
CPC classification number: G06F9/268 , G06F9/30029
Abstract: PURPOSE: An interrupt processing system is provided to improve the system efficiency by generating an interrupt signal only in a certain circumference. CONSTITUTION: Interrupt sources(241-24n) generate an interrupt signal. When the interrupt signal is activated, complex interrupt generators(231-23m) generate active complex interrupt signal. A logic operation unit generates the complex interrupt signal by performing an AND or OR operation according to a mode selection signal. Interrupt signal receivers detect the logic state of interrupt signals in consideration of a first control signal, and transfers the logic state to the operation unit selectively in consideration of the second control signal.
Abstract translation: 目的：提供中断处理系统，通过仅在一定周长内产生中断信号来提高系统效率。 构成：中断源（241-24n）产生一个中断信号。 当中断信号被激活时，复杂的中断发生器（231-23m）产生有效的复合中断信号。 逻辑运算单元通过根据模式选择信号执行“与”或“或”运算来生成复合中断信号。 考虑到第一控制信号，中断信号接收器检测中断信号的逻辑状态，并考虑到第二控制信号选择性地将逻辑状态传送到操作单元。
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