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公开(公告)号：KR101363174B1
公开(公告)日：2014-02-13
申请号：KR1020090075209
申请日：2009-08-14
Applicant: 한국전자통신연구원
CPC classification number: H03F3/24 , H03F1/565 , H03F3/195 , H03F2200/222
Abstract: 본 발명은 전력 증폭기는 게이트 단으로 입력된 신호를 증폭하여 드레인 단으로 출력하는 고전자 이동도 트랜지스터(HEMT)와, 상기 게이트 단과 접지 사이에 연결되는 입력 정합 회로와, 그리고 상기 드레인 단과 접지 사이에 연결되는 직류 바이어스 회로를 포함한다.
상술한 구성을 통하여 음전압을 제공하기 위한 바이어스 수단 없이, 단일 직류 바이어스 회로만으로 고전자 이동도 트랜지스터(HEMT)를 바이어스 할 수 있다. 또한, 션트 인덕터와 초크 인덕터를 통하여 다양한 동작 주파수 대역에서 우수한 정합 특성이 제공될 수 있다.-
公开(公告)号：KR101243836B1
公开(公告)日：2013-03-20
申请号：KR1020090083600
申请日：2009-09-04
Applicant: 한국전자통신연구원
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/8128 , H01L29/42316 , H01L29/66863
Abstract: 반도체 소자 및 그 형성 방법이 제공된다. 상기 반도체 소자는 기판, 기판 상에 배치되 게이트 전극의 양 측벽 상에 각각 배치된 제1 보이드 영역 및 제2 보이드 영역을 포함하고, 상기 게이트 전극의 양 측벽 상에 배치된 비대칭 보이드 영역으로 인해 특성이 우수한 반도체 소자가 제공될 수 있다.
T 형 게이트 전극, 보이드, 비대칭-
公开(公告)号：KR1020100061607A
公开(公告)日：2010-06-08
申请号：KR1020080120192
申请日：2008-11-29
Applicant: 한국전자통신연구원
IPC: G02B6/10 , H01L27/146
CPC classification number: H01L25/167 , H01L2224/0603 , H01L2224/45014 , H01L2224/48137 , H01L2224/4903 , H01L2224/73265 , H01L2924/1305 , H01L2924/30107 , H01L2924/00
Abstract: PURPOSE: A high speed optical wiring element is provided to form an optical has high speed, low power, and low price without a serializer, a parallelizer, and a modulator by using a multi-channel fiber. CONSTITUTION: A first semiconductor chip(301) is formed on a SOI(Silicon On Insulator) substrate(200). An optical emitter(302) outputs a multiple optical signal by receiving a multiple electric signal from the first semiconductor chip on the SOI substrate. An optical detector(304) changes the multi optical signal of the SOI substrate into the multiple electric signal. A second semiconductor chip(305) receives a multiple electric signal transformed with the optical detector of the SOI substrate. The SOI substrate comprises a first SOI substrate, a second semiconductor chip, and a second SOI substrate. The first SOI substrate and the second SOI substrate are arranged to be separated.
Abstract translation: 目的：通过使用多通道光纤，提供高速光配线元件以形成具有高速度，低功率和低价格的光学，而不需要串行器，并行器和调制器。 构成：在SOI（绝缘体上硅）衬底（200）上形成第一半导体芯片（301）。 光发射器（302）通过从SOI衬底上的第一半导体芯片接收多个电信号来输出多个光信号。 光检测器（304）将SOI衬底的多光信号改变为多电信号。 第二半导体芯片（305）接收用SOI衬底的光检测器变换的多电信号。 SOI衬底包括第一SOI衬底，第二半导体芯片和第二SOI衬底。 第一SOI衬底和第二SOI衬底被布置成分离。
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公开(公告)号：KR1020090059795A
公开(公告)日：2009-06-11
申请号：KR1020070126841
申请日：2007-12-07
Applicant: 한국전자통신연구원
IPC: H01L21/3205 , H01L21/28 , H01L21/768
CPC classification number: H01L21/76877 , H01L21/0274 , H01L21/31144 , H01L21/76802 , H01L21/76897
Abstract: A manufacturing method of a multilayer metal wiring is provided to stably manufacture a multilayer metal wiring and to reduce possibility of misalignment by forming a pattern through one exposure. A source drain ohmic metal layer is formed by depositing an ohmic metal(130) on a semiconductor substrate having an active layer and a cap layer. A first insulation film(140) is deposited on a whole surface of the semiconductor substrate. A first multilayer photoresist is deposited in consideration of an etching selection ratio with the first insulation film. A first metal wiring(170a) is formed by depositing a metal on a first pattern region. A second insulation film(180) is formed on a whole surface of the substrate having the first metal wiring. A second multilayer photoresist(150b,160b) is deposited in consideration of an etching selection ratio with the second insulation film. A second metal wiring(170b) is formed by depositing a metal on a second pattern region. A protective film is deposited on the second metal wiring.
Abstract translation: 提供多层金属布线的制造方法，以稳定地制造多层金属布线，并通过一次曝光形成图案来减少不对准的可能性。 源极欧姆金属层通过在具有有源层和盖层的半导体衬底上沉积欧姆金属（130）而形成。 第一绝缘膜（140）沉积在半导体衬底的整个表面上。 考虑到与第一绝缘膜的蚀刻选择比，沉积第一多层光致抗蚀剂。 通过在第一图案区域上沉积金属来形成第一金属布线（170a）。 在具有第一金属布线的基板的整个表面上形成第二绝缘膜（180）。 考虑到与第二绝缘膜的蚀刻选择比，沉积第二多层光致抗蚀剂（150b，160b）。 通过在第二图案区域上沉积金属来形成第二金属布线（170b）。 保护膜沉积在第二金属布线上。
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公开(公告)号：KR1020080052223A
公开(公告)日：2008-06-11
申请号：KR1020070054263
申请日：2007-06-04
Applicant: 한국전자통신연구원
IPC: H01L31/10
CPC classification number: H01L31/10 , H01L31/022425 , H01L31/02366 , H01L31/03046 , H01L31/18
Abstract: A Pin photodiode is provided to reduce the leakage current of a pin photodiode with a wave guide by forming a metal layer on a wafer guide pattern. A first semiconductor layer, an absorption layer, a second semiconductor layer, a photo clad layer and a photo cap layer are formed on a substrate(31). After a first insulation layer is formed on the photo cap layer, the first insulation layer is patterned by using a photoresist pattern formed on the first insulation layer. The photo cap layer, the photo clad layer, the second semiconductor layer and the absorption layer are etched by using the patterned first insulation layer as a mask. After the pattern first insulation layer is removed, a second insulation layer is formed on the patterned photo cap layer and the patterned first semiconductor layer. After a photoresist pattern is formed on the second insulation layer, the second insulation layer is patterned by using the photoresist pattern. The semiconductor layer is patterned by using the patterned second insulation layer. After the patterned second insulation layer is removed, a first electrode(41) is formed on the photo cap layer and the first semiconductor layer. After a polyimide layer can be formed on a partial region of the substrate, the polyimide layer is patterned and a second electrode(43) is formed on the patterned polyimide layer.
Abstract translation: 提供引脚光电二极管，通过在晶片引导图案上形成金属层来减小波导管的引脚光电二极管的漏电流。 在基板（31）上形成有第一半导体层，吸收层，第二半导体层，光覆层和光电盖层。 在光罩层上形成第一绝缘层之后，通过使用形成在第一绝缘层上的光致抗蚀剂图案来对第一绝缘层进行构图。 通过使用图案化的第一绝缘层作为掩模来蚀刻光封层，光覆层，第二半导体层和吸收层。 在去除图案第一绝缘层之后，在图案化的光罩层和图案化的第一半导体层上形成第二绝缘层。 在第二绝缘层上形成光致抗蚀剂图案之后，通过使用光致抗蚀剂图案来对第二绝缘层进行图案化。 通过使用图案化的第二绝缘层来图案化半导体层。 在去除图案化的第二绝缘层之后，在光电帽层和第一半导体层上形成第一电极（41）。 在可以在基板的部分区域上形成聚酰亚胺层之后，对该聚酰亚胺层进行图案化，并且在图案化的聚酰亚胺层上形成第二电极（43）。
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Patent Agency Ranking
公开(公告)号：KR100497840B1
公开(公告)日：2005-06-29
申请号：KR1020020083751
申请日：2002-12-24
Applicant: 한국전자통신연구원
IPC: H01L29/737
Abstract: 본 발명은 기판위에 복수의 층을 가진 이종접합 바이폴라 트랜지스터(HBT : heterojunction bipolar transistor) 제조용 웨이퍼를 식각하여 위로부터 에미터, 베이스 및 콜렉터를 갖는 HBT를 제조하는 방법에 있어서, HBT 제조용 웨이퍼는 에미터 층 및 베이스층 사이에 에미터 층과는 다른 재질의 제1식각 정지층을 가지며, 콜렉터 층 및 서브 콜렉터층 사이에 콜렉터 층과는 다른 재질의 제2식각 정지층을 가지고, 콜렉터 층과 제1식각 정지층에 대하여 선택적 식각 능력을 가진 식각 용액을 사용하여 콜렉터층을 식각함으로써 베이스 금속 전극 하부에 언더컷(undercut)을 형성시키고, 그 후 제1식각정지층을 식각하는 단계를 포함함을 특징으로 하는 HBT의 제조 방법, 그 방법에 제조된 HBT 및 상기 HBT의 제조에 사용될 수 있는 다층 웨이퍼에 관한 것이다. 본 발명에 따른 HBT는 제 2식각정지층을 이용하여 충분한 언더컷 확보로 인한 에미터 전극에 자기정렬된 베이스 금속 상에 콜렉터 금속 증착시 콜렉터 금속의 증착으로 인한 베이스 금속층의 두꺼워짐 및 에미터-베이스간의 거리 감소로 인하여 베이스 저항을 감소시키고, 제 1 식각정지층을 이용하여콜렉터 금속전극을 베이스 금속전극에 자기정렬시키므로써 베이스와 콜렉터간의 접합면적을 감소시켜 베이스-콜렉터의 기생 캐패시턴스를 감소시킬 수 있으며, 이로 인하여 고주파 특성을 향상시킬 수 있다.
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公开(公告)号：KR100444820B1
公开(公告)日：2004-08-18
申请号：KR1020010047655
申请日：2001-08-08
Applicant: 한국전자통신연구원
IPC: H01L31/12
Abstract: PURPOSE: A photodetector is provided to minimize a tunneling leakage current and improve the capability of a light receiving chip in which the photodetector and a hetero-junction bipolar transistor are integrated into a single chip, by smoothly transferring the charges generated in a light absorbing layer. CONSTITUTION: The first conductive layer of the first conductivity type is formed in a predetermined region on a substrate(40). A light absorbing layer(43) is stacked on the first conductive layer. The second conductive layer of the second conductivity type is stacked on the light absorbing layer. The third conductive layer are formed between the first conductive layer and the light absorbing layer and between the light absorbing layer and the second conductive layer, decreasing a lattice match and a potential energy band difference between the two stack layers to make photoelectrons flow smoothly.
Abstract translation: 目的：提供一种光电探测器，以最小化隧道泄漏电流，并通过将光吸收层中产生的电荷平稳地转移到光电探测器中，从而提高其中光电探测器和异质结双极晶体管集成到单个芯片中的光接收芯片的能力 。 构成：第一导电类型的第一导电层形成在衬底（40）上的预定区域中。 光吸收层（43）堆叠在第一导电层上。 第二导电类型的第二导电层堆叠在光吸收层上。 所述第三导电层形成于所述第一导电层与所述光吸收层之间以及所述光吸收层与所述第二导电层之间，减少所述两层叠层之间的晶格匹配和势能差，使光电子顺利流动。
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公开(公告)号：KR100440431B1
公开(公告)日：2004-07-14
申请号：KR1020020071501
申请日：2002-11-18
Applicant: 한국전자통신연구원
IPC: G02B6/12
Abstract: PURPOSE: A submount for electro optical device of a high speed electro optical module is provided to reduce the transmission loss and the reflection loss of the data by drastically reducing the parasitic effect remained at the peripheral of the wire bonding. CONSTITUTION: A submount for electro optical device of a high speed electro optical module includes a dielectric material(20), a pair of ground lines(22a,22c), a signal line(22b), a bias line(22d), a ground plane(28) and a via hole. The dielectric material(20) is in the shape of "L". The pair of ground lines(22a,22c), the signal line(22b) and the bias line(22d) are stacked on the top surface of the dielectric material(20) by using a co-planar waveguide-ground(CPW-G). The ground plane(28) is positioned inside of the dielectric material(20). And, the via hole is connected the ground lines(22a,22c) to the ground plane(28).
Abstract translation: 目的：提供一种高速电光学组件的电子光学装置的基座，通过大幅度降低导线键合周边残留的寄生效应，减少数据的传输损耗和反射损耗。 本发明提供一种高速电光学模块的电光学装置的基座，其包括介电材料20，一对接地线22a，22c，信号线22b，偏压线22d， 平面（28）和通孔。 介电材料（20）呈“L”形。 通过使用共面波导接地（CPW-G）将一对接地线（22a，22c），信号线（22b）和偏置线（22d）堆叠在介电材料（20）的顶表面上 ）。 接地平面（28）位于电介质材料（20）的内部。 并且，通孔将接地线（22a，22c）连接到接地平面（28）。
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公开(公告)号：KR1020040053486A
公开(公告)日：2004-06-24
申请号：KR1020020080045
申请日：2002-12-14
Applicant: 한국전자통신연구원
IPC: H03F3/45
Abstract: PURPOSE: A transimpedance amplifier for high-speed optical receiver is provided to enlarge a frequency band and lower the loss of the input/output reflection by performing an amplifying process twice and feeding back the amplified signal. CONSTITUTION: A transimpedance amplifier for high-speed optical receiver includes the first amplifier, the second amplifier, a feedback circuit, and a buffer. The first amplifier(110) is used for converting an optical current to a voltage and amplifying the converted voltage. The second amplifier(120) is used for amplifying an output of the first amplifier. The feedback circuit(130) feeds back an output of the second amplifier to the first amplifier. The buffer(140) buffers an output signal of the feedback circuit.
Abstract translation: 目的：提供一种用于高速光接收机的跨阻放大器，通过进行两次放大处理并反馈放大信号来放大频带并降低输入/输出反射损耗。 构成：用于高速光接收器的跨阻放大器包括第一放大器，第二放大器，反馈电路和缓冲器。 第一放大器（110）用于将光电流转换成电压并放大转换的电压。 第二放大器（120）用于放大第一放大器的输出。 反馈电路（130）将第二放大器的输出反馈到第一放大器。 缓冲器（140）缓冲反馈电路的输出信号。
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公开(公告)号：KR1020040043282A
公开(公告)日：2004-05-24
申请号：KR1020020071501
申请日：2002-11-18
Applicant: 한국전자통신연구원
IPC: G02B6/12
Abstract: PURPOSE: A submount for electro optical device of a high speed electro optical module is provided to reduce the transmission loss and the reflection loss of the data by drastically reducing the parasitic effect remained at the peripheral of the wire bonding. CONSTITUTION: A submount for electro optical device of a high speed electro optical module includes a dielectric material(20), a pair of ground lines(22a,22c), a signal line(22b), a bias line(22d), a ground plane(28) and a via hole. The dielectric material(20) is in the shape of "L". The pair of ground lines(22a,22c), the signal line(22b) and the bias line(22d) are stacked on the top surface of the dielectric material(20) by using a co-planar waveguide-ground(CPW-G). The ground plane(28) is positioned inside of the dielectric material(20). And, the via hole is connected the ground lines(22a,22c) to the ground plane(28).
Abstract translation: 目的：提供高速电光模块的电子光学装置的底座，通过大大减少引线键合周边残留的寄生效应，减少数据的传输损耗和反射损耗。 构成：高速电光模块的电光装置用基座包括电介质材料（20），一对接地线（22a，22c），信号线（22b），偏置线（22d），接地 平面（28）和通孔。 电介质材料（20）为“L”形。 该一对接地线（22a，22c），信号线（22b）和偏置线（22d）通过使用共面波导 - 接地（CPW-G）堆叠在电介质材料（20）的顶表面上 ）。 接地平面（28）位于电介质材料（20）的内部。 并且，通孔将接地线（22a，22c）连接到接地平面（28）。
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